A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path

Abstract

With the widespread applications of wireless sensors, implantable biomedical devices, and small handheld devices, the demand for ultra-low voltage SRAM is growing. However, the probability of soft errors at low voltages is also increasing, and using a bit-interleaving structure is essential for ultra-low voltage SRAM to mitigate soft errors efficiently. Nevertheless, the write half-select disturb, which results in unstable operation in the bit-interleaving structure, poses critical challenges to achieve faster writes at ultra-low voltages [1] –[5].