A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking

Abstract

High-end mobile devices are desired to support multiple radio standards across a large bandwidth and DR span, e.g., from GSM, BLE, NB-loT to 5G and WiFi-6, which impose great challenges on the receiver’s ADC design. Deploying specialized ADCs for every standard is beneficial in performance and power efficiency, but will soon become too costly and bulky as the number of standards explodes. Multi-mode or reconfigurable ADCs are promising solutions, as they adapt to different standards (i.e., different BW and DR) with reasonable efficiency. However, most of the prior multimode ADCs (e.g., [1]) are based on circuit-level tuning or DSM loop configuring, thus providing a narrow performance range and limited standard coverage. Besides, these designs are usually exclusive between modes and cannot simultaneously support multiple standards.