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2021 Symposium on VLSI Circuits最新文献

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A 1.5nJ/cls Unsupervised Online Learning Classifier for Seizure Detection 一种1.5nJ/cls的癫痫检测无监督在线学习分类器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492392
A. Chua, M. I. Jordan, R. Muller
{"title":"A 1.5nJ/cls Unsupervised Online Learning Classifier for Seizure Detection","authors":"A. Chua, M. I. Jordan, R. Muller","doi":"10.23919/VLSICircuits52068.2021.9492392","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492392","url":null,"abstract":"This work presents a 1.5 nJ/classification (nJ/cls) seizure detection classifier which provides unsupervised online updates on an initial offline-trained regression model to achieve >97% average sensitivity and specificity on 27 patient datasets, including three that have >250 hours of continuous recording. The classifier was fabricated in 28nm CMOS and operates at 0.5V supply. Through hardware optimizations and low overall computational complexity and voltage scaling, the online learning classifier achieves 24× better energy per classification and occupies 10x lower area than state-of-the-art.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems 基于边缘计算的监控摄像系统的CMOS图像传感器和AI加速器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492514
F. Morishita, Norihito Kato, S. Okubo, T. Toi, M. Hiraki, S. Otani, Hideaki Abe, Yuji Shinohara, H. Kondo
{"title":"A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems","authors":"F. Morishita, Norihito Kato, S. Okubo, T. Toi, M. Hiraki, S. Otani, Hideaki Abe, Yuji Shinohara, H. Kondo","doi":"10.23919/VLSICircuits52068.2021.9492514","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492514","url":null,"abstract":"This paper presents a CMOS image sensor and an AI accelerator to realize surveillance camera systems based on edge computing. For CMOS image sensors to be used for surveillance, it is desirable that they are highly sensitive even in low illuminance. We propose a new timing shift ADC used in CMOS image sensors for improving high sensitivity performance. Our proposed ADC improves non-linearity characteristics under low illuminance by 63%. Achieving power-efficient edge computing is a challenge for the systems to be used widely in the surveillance camera market. We demonstrate that our proposed AI accelerator performs inference processing for object recognition with 1 TOPS/W. Keywords: CMOS image sensor, surveillance camera system, low light imaging, AI accelerator, edge computing","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129136369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode 采用最小固有自对准和抗噪编码的7nm 0.46pJ/bit 20Gbps BER 1E-25模对模链路
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492439
Y. Hsu, Po-Chun Kuo, Chih-Lun Chuang, Po-Hao Chang, Hung-Hao Shen, Chen-Feng Chiang
{"title":"A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode","authors":"Y. Hsu, Po-Chun Kuo, Chih-Lun Chuang, Po-Hao Chang, Hung-Hao Shen, Chen-Feng Chiang","doi":"10.23919/VLSICircuits52068.2021.9492439","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492439","url":null,"abstract":"This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have been fabricated in TSMC 7nm FinFET 1P15M CMOS technology. Interconnection is demonstrated through TSMC Chip-on-Wafer-on-Substrate (CoWoS) and TSMC Integrated Fan-Out (InFO) packaging technology [1]. Mlink PHY exploits energy-efficient and high performance scheme, includes single-ended without termination, quarter rate strobe and unbalance scheme on transceiver, minimum intrinsic auto-alignment and novel noise-immunity coding methodology. Achieving 20Gb/s/wire and 0.46pJ/bit under 1-mm ultra-short-reach platform target to BER 1E-25. Bandwidth density is normalized with shoreline 5.31Tb/s/mm and area 2.25Tb/s/mm^2 respectively.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116654106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Program 程序
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492456
Juridiske Fakultet, Grundlæggende udbudsret, Carina Risvig Hamer
{"title":"Program","authors":"Juridiske Fakultet, Grundlæggende udbudsret, Carina Risvig Hamer","doi":"10.23919/VLSICircuits52068.2021.9492456","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492456","url":null,"abstract":"","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115326049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 650 pW, −71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques 基于曲率温度补偿和SBFL技术的650pw， - 71 dB PSRR, 205°C温度范围混合电压基准
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492407
Cheng-Ze Shao, Y. Liao
{"title":"A 650 pW, −71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques","authors":"Cheng-Ze Shao, Y. Liao","doi":"10.23919/VLSICircuits52068.2021.9492407","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492407","url":null,"abstract":"This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from −55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of −71 dB at 100 Hz by employing a self-biasing feedback loop.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access PNNPU:一个11.9 TOPS/W的高速3D点云神经网络处理器，具有基于块的点处理，用于常规DRAM访问
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492450
Sangjin Kim, Juhyoung Lee, Dongseok Im, H. Yoo
{"title":"PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access","authors":"Sangjin Kim, Juhyoung Lee, Dongseok Im, H. Yoo","doi":"10.23919/VLSICircuits52068.2021.9492450","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492450","url":null,"abstract":"An efficient and high-speed 3D point cloud-based neural network processing unit (PNNPU) is proposed using the block-based point processing. It has three key features: 1) page-based point block memory management unit (PMMU) with linked list-based page table (LLPT) for on-chip memory footprint reduction, 2) hierarchical block-wise farthest point sampling (HFPS), and block skipping ball-query (BSBQ) for fast and efficient point processing, 3) Skipping-based max-pooling prediction (SMPP) for throughput enhancement. The PNNPU is fabricated in 65nm CMOS process and evaluated on the 3D object detection (3D OD) application. As a result, it shows 84.8 fps at 266.8mW power consumption and achieving 6.6-11.9 TOPS/W energy efficiency.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121568648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
First InGaAs/InAlAs Single-Photon Avalanche Diodes (SPADs) Heterogeneously Integrated with Si Photonics on SOI Platform for 1550 nm Detection 在SOI平台上首次将InGaAs/InAlAs单光子雪崩二极管(spad)与Si光子学异质集成，用于1550 nm检测
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492337
Jishen Zhang, Haiwen Xu, Gong Zhang, Yue Chen, Haibo Wang, K. Tan, S. Wicaksono, Chao Wang, Chen Sun, Qiwen Kong, C. Lim, S. Yoon, Xiao Gong
{"title":"First InGaAs/InAlAs Single-Photon Avalanche Diodes (SPADs) Heterogeneously Integrated with Si Photonics on SOI Platform for 1550 nm Detection","authors":"Jishen Zhang, Haiwen Xu, Gong Zhang, Yue Chen, Haibo Wang, K. Tan, S. Wicaksono, Chao Wang, Chen Sun, Qiwen Kong, C. Lim, S. Yoon, Xiao Gong","doi":"10.23919/VLSICircuits52068.2021.9492337","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492337","url":null,"abstract":"For the first time, heterogeneous integration of InGaAs/InAlAs single-photon avalanche diodes (SPADs) with Si photonics was realized and demonstrated through a low temperature die-to-die bonding technique. Together with the adoption of a triple-mesa structure in SPADs which not only avoids the surface exposure to the high electric field but also alleviate the electric field crowding at mesa edges, our integrated SPADs exhibit high single-photon detection efficiency (SPDE) of ~22% and low dark count rate (DCR) of 8.6 ×105 Hz, which are among the best performance reported for InGaAs/InAlAs SPADs, and are approaching that of InGaAs/InP SPADs. High device yield and performance uniformity were also achieved.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
First Demonstration of Waveguide-Coupled Ge0.92Sn0.08/Ge Multiple-Quantum-Well Photodetector on the SOI Platform for 2-μm Wavelength Optoelectronic Integrated Circuit 2 μm波长光电集成电路波导耦合Ge0.92Sn0.08/Ge多量子阱光电探测器在SOI平台上的首次演示
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492371
Haibo Wang, Yue Chen, Jishen Zhang, Gong Zhang, Yi-Chiau Huang, Xiao Gong
{"title":"First Demonstration of Waveguide-Coupled Ge0.92Sn0.08/Ge Multiple-Quantum-Well Photodetector on the SOI Platform for 2-μm Wavelength Optoelectronic Integrated Circuit","authors":"Haibo Wang, Yue Chen, Jishen Zhang, Gong Zhang, Yi-Chiau Huang, Xiao Gong","doi":"10.23919/VLSICircuits52068.2021.9492371","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492371","url":null,"abstract":"We report the first demonstration of a silicon-on-insulator (SOI) waveguide-coupled Ge0.92Sn0.08/Ge multiple-quantum-well (MQW) photodiode (PD) for 2 μm wavelength using a flip-chip bonding technology. The light in the waveguide couples to the PD for detection via a grating coupler. The grating coupler and waveguide were designed and fabricated on the standard SOI wafer for 2 μm and bonded with the GeSn/Ge PDs. On the same wafer, back illuminated GeSn/Ge PDs were also integrated using the same technology for free space optical detection. Our waveguide-coupled PD exhibits responsivity of 10.3 mA/W at 2 μm wavelength and one of the lowest dark current densities of 38.4 mA/cm2 for Ge1-xSnx PDs. In addition, no degradation of the dark current was found after the bonding.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116634657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A SiPM Readout IC Embedded in a Boost Converter for Mobile Dosimeters 一种嵌入在移动剂量计升压变换器中的SiPM读出集成电路
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492346
Hyuntak Jeon, Injun Choi, Young-Han Kim, Se-un Shin, M. Je
{"title":"A SiPM Readout IC Embedded in a Boost Converter for Mobile Dosimeters","authors":"Hyuntak Jeon, Injun Choi, Young-Han Kim, Se-un Shin, M. Je","doi":"10.23919/VLSICircuits52068.2021.9492346","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492346","url":null,"abstract":"A power-and hardware-efficient radiation detection system is presented for mobile dosimeter. Thanks to the duty quantizer embedded in boost converter for driving radiation detector, the radiation signal can be converted to digital value without implementing seabsparate sensor interface circuits. The prototype IC is implemented using 0.18-µm BCD process, and achieves 0.217µArms of integrated input referred noise enough low to measure radiation signal without using complex readout IC.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123367644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS 一个122-168GHz雷达/通信融合模式收发器，30GHz啁啾带宽，13dBm Psat和8.3dBm OP1dB在28nm CMOS
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492460
Zipeng Chen, W. Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, B. Chi
{"title":"A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS","authors":"Zipeng Chen, W. Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, B. Chi","doi":"10.23919/VLSICircuits52068.2021.9492460","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492460","url":null,"abstract":"A D-band radar/communication fusion-mode transceiver featuring dual-function multiplexers, a two-point modulation (TPM) FMCW digital PLL with a dual-core DCO, wideband I/Q LO generators, current choking high-gain mixers, and a power-combining PA with high output power is implemented in 28nm CMOS. In the radar mode, the RF front-end demonstrates 46GHz bandwidth, and the on-chip PLL/LO generated FMCW chirp achieves a wide bandwidth of 30GHz and a fast slope of 30GHz/50μs. In the communication mode, the transceiver including analog baseband realizes 20GHz BW and the IRR is better than 40dB. The measured TX saturated Pout is 13 dBm and output P1dB is 8.3 dBm. The measured PLL phase noise is -112dBc/Hz at 1MHz offset from the 11.69GHz carrier. The TX-to-RX over-the-air (OTA) modulation-demodulation measurement with QPSK and 16QAM signals shows the EVM of -20.7dB and -19.7dB, respectively.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"11 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120972660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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