采用最小固有自对准和抗噪编码的7nm 0.46pJ/bit 20Gbps BER 1E-25模对模链路

Y. Hsu, Po-Chun Kuo, Chih-Lun Chuang, Po-Hao Chang, Hung-Hao Shen, Chen-Feng Chiang
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引用次数: 5

摘要

这项工作提出了一个高密度低误码率和低功耗的Mlink(联发科链路)PHY,用于超短距离(USR)模对模通信。提出的Mlink采用TSMC 7nm FinFET 1P15M CMOS技术制造。互连通过TSMC Chip-on-Wafer-on-Substrate (coos)和TSMC Integrated Fan-Out (InFO)封装技术进行演示[1]。Mlink PHY利用节能和高性能的方案,包括单端无终端,收发器上的四分之一速率频闪和不平衡方案,最小固有自对准和新颖的抗噪声编码方法。在1毫米超短距离平台下实现20Gb/s/线和0.46pJ/bit的BER 1E-25目标。带宽密度分别以海岸线5.31Tb/s/mm和面积2.25Tb/s/mm^2归一化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode
This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have been fabricated in TSMC 7nm FinFET 1P15M CMOS technology. Interconnection is demonstrated through TSMC Chip-on-Wafer-on-Substrate (CoWoS) and TSMC Integrated Fan-Out (InFO) packaging technology [1]. Mlink PHY exploits energy-efficient and high performance scheme, includes single-ended without termination, quarter rate strobe and unbalance scheme on transceiver, minimum intrinsic auto-alignment and novel noise-immunity coding methodology. Achieving 20Gb/s/wire and 0.46pJ/bit under 1-mm ultra-short-reach platform target to BER 1E-25. Bandwidth density is normalized with shoreline 5.31Tb/s/mm and area 2.25Tb/s/mm^2 respectively.
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