A 650 pW, −71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques

Abstract

This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from −55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of −71 dB at 100 Hz by employing a self-biasing feedback loop.