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M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay M-IVC:使用多输入向量最小化老化引起的延迟
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.57
Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan
{"title":"M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay","authors":"Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan","doi":"10.1109/ATS.2009.57","DOIUrl":"https://doi.org/10.1109/ATS.2009.57","url":null,"abstract":"Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115961691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Test Integration for SOC Supporting Very Low-Cost Testers 测试集成的SOC支持非常低成本的测试仪
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.51
Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
{"title":"Test Integration for SOC Supporting Very Low-Cost Testers","authors":"Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu","doi":"10.1109/ATS.2009.51","DOIUrl":"https://doi.org/10.1109/ATS.2009.51","url":null,"abstract":"To reduce test cost for SOC products, it is important to reduce the cost of testers. When using low-cost testers which have a limited test bandwidth to perform testing, Built-In- Self-Test (BIST) is necessary to reduce the data volume to be transmitted between the tester and the device-under-test (DUT). We enhance the SOC test integration tool, STEAC, so that it can support SOCs containing BISTed cores which are to be tested by low-cost testers. A test chip is implemented to verify the proposed technique. Experimental results show that the enhanced STEAC successfully works with the HOY wireless test system and other low-cost testers.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE 利用过零技术分析调频调制模拟/射频信号的数字ATE
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.56
N. Pous, F. Azaïs, L. Latorre, P. Nouet, J. Rivoir
{"title":"Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE","authors":"N. Pous, F. Azaïs, L. Latorre, P. Nouet, J. Rivoir","doi":"10.1109/ATS.2009.56","DOIUrl":"https://doi.org/10.1109/ATS.2009.56","url":null,"abstract":"This paper presents a reconstruction technique based on zero-crossing detection that permits analyzing FM-modulated signals using digital ATE channels. The technique relies on sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. The proposed solution is validated through both simulation and hardware experiments.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125589507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On the Generation of Functional Test Programs for the Cache Replacement Logic 缓存替换逻辑功能测试程序的生成研究
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.37
H. WilsonJ.Pérez, D. Ravotto, E. Sánchez, M. Reorda, A. Tonda
{"title":"On the Generation of Functional Test Programs for the Cache Replacement Logic","authors":"H. WilsonJ.Pérez, D. Ravotto, E. Sánchez, M. Reorda, A. Tonda","doi":"10.1109/ATS.2009.37","DOIUrl":"https://doi.org/10.1109/ATS.2009.37","url":null,"abstract":"Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-frequency devices. While the test of the memory array within the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce. In this paper we face the issue of generating suitable programs for testing the replacement logic in set-associative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to assess the effectiveness of the method.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127803778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification 基于感测放大的3D集成电路键合前片上TSV测试
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.42
Po-Yuan Chen, Cheng-Wen Wu, D. Kwai
{"title":"On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification","authors":"Po-Yuan Chen, Cheng-Wen Wu, D. Kwai","doi":"10.1109/ATS.2009.42","DOIUrl":"https://doi.org/10.1109/ATS.2009.42","url":null,"abstract":"We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 142
Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug 在基于跟踪缓冲的硅调试中使用非平凡逻辑含义
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.20
S. Prabhakar, M. Hsiao
{"title":"Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug","authors":"S. Prabhakar, M. Hsiao","doi":"10.1109/ATS.2009.20","DOIUrl":"https://doi.org/10.1109/ATS.2009.20","url":null,"abstract":"An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing the number of signals traced and maximizing the observability/restorability of other untraced signals during post-silicon validation. This paper presents a new method for trace buffer signal selection for the purpose of post-silicon debug. The selection is performed by favoring those signals with the most number of implications that are not implied by other signals. Then, based on the values of the traced signals during silicon debug, we introduce an algorithm which uses a SAT-based multi-node implication engine to restore the values of untraced signals across multiple time-frames. Experimental results for sequential benchmark circuits showed that the proposed approach selects the trace signals effectively, giving a high restoration percentage compared with other techniques.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
A Jitter Characterizing BIST with Pulse-Amplifying Technique 用脉冲放大技术表征BIST的抖动
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.23
An-Sheng Chao, Soon-Jyh Chang
{"title":"A Jitter Characterizing BIST with Pulse-Amplifying Technique","authors":"An-Sheng Chao, Soon-Jyh Chang","doi":"10.1109/ATS.2009.23","DOIUrl":"https://doi.org/10.1109/ATS.2009.23","url":null,"abstract":"A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testing time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 X 0.336 mm2 in a 0.18-um CMOS process.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129285327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On Scan Chain Diagnosis for Intermittent Faults 间歇故障的扫描链诊断
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.74
Dan Adolfsson, J. Siew, E. Marinissen, E. Larsson
{"title":"On Scan Chain Diagnosis for Intermittent Faults","authors":"Dan Adolfsson, J. Siew, E. Marinissen, E. Larsson","doi":"10.1109/ATS.2009.74","DOIUrl":"https://doi.org/10.1109/ATS.2009.74","url":null,"abstract":"Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116870218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
New Class of Tests for Open Faults with Considering Adjacent Lines 考虑相邻线路的新一类开放故障试验
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.39
Hiroshi Takahashi, Y. Higami, Y. Takamatsu, K. Yamazaki, Toshiyuki Tsutsumi, H. Yotsuyanagi, M. Hashizume
{"title":"New Class of Tests for Open Faults with Considering Adjacent Lines","authors":"Hiroshi Takahashi, Y. Higami, Y. Takamatsu, K. Yamazaki, Toshiyuki Tsutsumi, H. Yotsuyanagi, M. Hashizume","doi":"10.1109/ATS.2009.39","DOIUrl":"https://doi.org/10.1109/ATS.2009.39","url":null,"abstract":"Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters cite{yanagi09, yamazaki09, tsume08}.In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Practical DFT Approach for Complex Low Power Designs 复杂低功耗设计的实用DFT方法
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.61
A. Kifli, Y. W. Chen, Yu-Wen Tsai, Kun-Cheng Wu
{"title":"A Practical DFT Approach for Complex Low Power Designs","authors":"A. Kifli, Y. W. Chen, Yu-Wen Tsai, Kun-Cheng Wu","doi":"10.1109/ATS.2009.61","DOIUrl":"https://doi.org/10.1109/ATS.2009.61","url":null,"abstract":"Low power designs create new challenges in design implementation, verification and testing. DFT practice that overlooks test power may result in yield loss/overkill during manufacturing test. This paper addresses the practical problems often encountered during DFT implementation and manufacturing test for complex low power designs.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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