IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications最新文献

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Resynchronization for multiprocessor DSP systems 多处理器DSP系统的再同步
S. Bhattacharyya, S. Sriram, Edward A. Lee
{"title":"Resynchronization for multiprocessor DSP systems","authors":"S. Bhattacharyya, S. Sriram, Edward A. Lee","doi":"10.1109/81.895327","DOIUrl":"https://doi.org/10.1109/81.895327","url":null,"abstract":"This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICs, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced. Our study is based on the context of self-timed execution for iterative dataflow specifications of DSP applications. An iterative dataflow specification consists of a dataflow representation of the body of a loop that is to be iterated indefinitely; dataflow programming in this form has been employed extensively in the DSP domain.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122257006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Self-control of chaotic dynamics using LTI filters 使用LTI滤波器的混沌动力学自我控制
Pabitra Mitra
{"title":"Self-control of chaotic dynamics using LTI filters","authors":"Pabitra Mitra","doi":"10.1109/81.895334","DOIUrl":"https://doi.org/10.1109/81.895334","url":null,"abstract":"In this brief, an algorithm for controlling chaotic systems using small, continuous-time perturbations is presented. Stabilization is achieved by self controlling feedback using low order LTI filters. The algorithm alleviates the need of complex calculations or costly delay elements and can be implemented in a wide variety of systems using simple circuit elements only.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A robust algorithm for adaptive FIR filtering and its performance analysis with additive contaminated-Gaussian noise 一种鲁棒自适应FIR滤波算法及其加性高斯污染噪声的性能分析
S. Bang, S. Ann
{"title":"A robust algorithm for adaptive FIR filtering and its performance analysis with additive contaminated-Gaussian noise","authors":"S. Bang, S. Ann","doi":"10.1109/81.502204","DOIUrl":"https://doi.org/10.1109/81.502204","url":null,"abstract":"Abstruct- We introduce a steepest descent linear adaptive algorithm, the proportion-sign algorithm (PSA), lo make the least mean square (LMS) algorithm robust to impulsive interference occurring in the desired response. Its performance analysis is presented when the signals are from zero-mean jlointly stationary Gaussian processes and the additive noise to the (desired response is from a zero-mean stationary contaminated-Gaussian (CG) process which is usually used to represent impulsive interference. Since a special case of the PSA becomes the LMS algorithm, the analysis of the LMS is also obtained as a by-product. By adding a minimal amount of computational complexity, thie PSA improves to some degree the convergence speed over the LMS algorithm without overly degrading the steady-state error performance for Gaussian noise. In addition, since the first derivative of its cost function with respect to estimation error is bounded, it has the properties of robustness to impulsive interference occurring in the desired response while the LMS algorithm is vulnerable to it. Computer simulations are used to demonstrate the validity of our analysis and the robustness of the PSA compared with the LMS algorithm.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132551077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Minimization of the 0-1 linear programming problem under linear constraints by using neural networks: synthesis and analysis 用神经网络求解线性约束下的0-1线性规划问题:综合与分析
M. Aourid, B. Kaminska
{"title":"Minimization of the 0-1 linear programming problem under linear constraints by using neural networks: synthesis and analysis","authors":"M. Aourid, B. Kaminska","doi":"10.1109/81.502215","DOIUrl":"https://doi.org/10.1109/81.502215","url":null,"abstract":"In this brief, we propose a new design: a Boolean Neural Network (BNN) for the 0-1 linear programming problem under inequalities constraints by using the connection between concave programming and integer programming problems. This connection is based on the concavity and penalty function methods. The general objective function obtained, which combines the objective function and constraints is fixed as the energy of the system. The simulation results for the new BNN show that the system converge rapidly within a few neural time constant.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Statistical techniques for the computer-aided optimization of analog integrated circuit 模拟集成电路计算机辅助优化的统计技术
C. Michael, H. Su, Mohammed Ismail, Antti Kankunnen, Martti Valtonen
{"title":"Statistical techniques for the computer-aided optimization of analog integrated circuit","authors":"C. Michael, H. Su, Mohammed Ismail, Antti Kankunnen, Martti Valtonen","doi":"10.1109/81.502212","DOIUrl":"https://doi.org/10.1109/81.502212","url":null,"abstract":"A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127195380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The dynamic range of second-order continuous-time active filters 二阶连续有源滤波器的动态范围
P. Bowron, K. Mezher, A. A. Muhieddine
{"title":"The dynamic range of second-order continuous-time active filters","authors":"P. Bowron, K. Mezher, A. A. Muhieddine","doi":"10.1109/81.502205","DOIUrl":"https://doi.org/10.1109/81.502205","url":null,"abstract":"Analysis of both the output noise and the large-signal harmonic distortion in terms of block diagrams allows the total dynamic range of active filters to be predicted theoretically. This leads to optimization and comparison of single and multiple-amplifier RC and OTA-C second-order bandpass filter circuits. The results are confirmed experimentally throughout. Increased design frequency or selectivity reduces dynamic range which is also often related to active sensitivity. Available OTA-C circuits appear to pay for their higher-frequency performance in terms of more restricted signal-handling capability.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121435260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Occasional linear connection for synchronization of chaos 混沌同步的偶尔线性连接
H. Torikai, T. Saito
{"title":"Occasional linear connection for synchronization of chaos","authors":"H. Torikai, T. Saito","doi":"10.1109/81.502206","DOIUrl":"https://doi.org/10.1109/81.502206","url":null,"abstract":"This paper considers synchronization of chaos from a simple piecewise linear continuous-time circuit. The chaotic circuit includes a bipolar hysteresis element whose thresholds vary periodically and we can prove observable chaos generation by using one-dimensional return map. Then we propose the occasional linear connection method (ab. OLC) that can realize three kinds of master-slave synchronous states of chaos (in-phase, lagging-phase, and leading-phase synchronous states) and in-phase mutual synchronization of chaos. The OLC is a novel nonlinear method that connects chaos generators by using periodically sampled error, only if the objective states are trapped into some linear region. Then we have given a theoretical evidence for the OLC function. Moreover, we propose a simple implementation example of the OLC and demonstrate its basic performance.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Time domain characteristics of rational systems with scale-invariant frequency response 具有标度不变频率响应的有理系统的时域特性
G. Maskarinec, B. Onaral
{"title":"Time domain characteristics of rational systems with scale-invariant frequency response","authors":"G. Maskarinec, B. Onaral","doi":"10.1109/81.502209","DOIUrl":"https://doi.org/10.1109/81.502209","url":null,"abstract":"The class of rational systems characterized by a magnitude response which is scale invariant for a specific scale change, or equivalently γ-homogeneous rational systems, are useful in modeling power-law processes. Such systems can be constructed by cascading frequency-scaled replicas of a prototype rational function which satisfies certain conditions. In this communication, we study the time domain characteristics of such systems. We show that, in the case of degree-1 or degree-2 prototypes, the magnitudes of the partial fraction expansion coefficients constitute a geometric sequence. Furthermore, in the degree-2 case, the angles of the partial fraction expansion coefficients are equal. Using these properties, we demonstrate that the impulse response of a e, γ-homogeneous rational system is essentially a linear combination of dilations of a prototype waveform and therefore exhibits a wavelet-like decomposition.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On taming chaos using LTI filters 用LTI滤波器驯服混沌
C. Piccardi
{"title":"On taming chaos using LTI filters","authors":"C. Piccardi","doi":"10.1109/81.502218","DOIUrl":"https://doi.org/10.1109/81.502218","url":null,"abstract":"In a recent paper [l] the possibility of suppressing chaos using linear time-invariant (LTI) filters is considered with numerical experiments concerning a specific chaotic system (the logistic map) and low-order filters. In this letter, simple arguments based on the frequency response of linear systems and on the Liapunov exponents are used to point out that the experimental result of [l] (i.e., a low-order LTI filter cannot destroy nor delay chaos in the logistic map) has general validity, namely it can be extended to any continuous or discrete-time chaotic system and to LTI filters of any order.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128316851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of an nth order Dickson voltage multiplier n阶迪克森电压倍增器的设计
G. Dicataldo, G. Palumbo
{"title":"Design of an nth order Dickson voltage multiplier","authors":"G. Dicataldo, G. Palumbo","doi":"10.1109/81.502213","DOIUrl":"https://doi.org/10.1109/81.502213","url":null,"abstract":"In this brief we propose a simple dynamic model of a Dickson voltage multiplier with N stages, which is obtained starting from the models previously proposed for less than 5 stages. The model allows increased insight into the dynamic behavior of these circuits and provides a valuable tool for determining a first version design.","PeriodicalId":104733,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127542505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
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