{"title":"Live demonstration: Using SIMULINK S-functions for the efficient modeling and simulation of analog integrated circuits and systems","authors":"J. M. Rosa","doi":"10.1109/ISCAS.2014.6865160","DOIUrl":"https://doi.org/10.1109/ISCAS.2014.6865160","url":null,"abstract":"This demo shows how to implement efficient behavioral modeling and simulation techniques for the systematic design of analog circuits and systems in MATLAB/SIMULINK. The methodology described in the demo is based on the use of C-coded SIMULINK S-functions to develop precise models of analog circuits, which allow designers to simulate complex systems with reduced simulation time, while keeping high accuracy. This simulation approach can be combined with an optimizer to automate the high-level synthesis and verification of many different analog integrated systems. As an application, two different toolboxes developed using the proposed techniques are illustrated in this demo: one is intended for the simulation of wireless receivers and the other one focuses on Σ∆ data converters. Through the multiple examples included in these toolboxes, visitors will experience the philosophy behind the presented approach and will learn how to apply it to their own designs and projects. ISCAS Track: Analog Signal Processing.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"437"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82388652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 9.4-bit, 28.8-mV range inverter based readout circuit for implantable pressure bridge piezo-resistive sensor","authors":"T. Nguyen, P. Häfliger","doi":"10.1109/ISCAS.2014.6865650","DOIUrl":"https://doi.org/10.1109/ISCAS.2014.6865650","url":null,"abstract":"This paper presents an energy efficient inverter based readout circuit for implantable pressure bridge piezo-resistive sensor which can achieve 9 bit resolution with 28.8-mV input voltage range. Only one bridge branch is utilized with interchanging supply voltage to achieve net differential input voltage range, hence reducing the power consumption by a half. A gain compensated technique is applied for inverter based switched capacitor amplifier to achieve both power efficiency and high resolution. A two-step auto calibration is applied to eliminate the offset from non-ideal effects of the switched-capacitor amplifier (SC-amp) and comparator delay. The readout system is implemented and simulated in TSMC 90 nm CMOS technology. With supply voltage of 1.2 V, simulation results show that the circuit can achieve 9.4 bit resolution while consuming only 35 μW during 320 μs conversion time. The digital output code has little sensitivity to temperature variation.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"24 1","pages":"2377-2380"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73249444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ziyou Yao, Weifeng He, L. Hong, Guanghui He, Zhigang Mao
{"title":"Area and throughput efficient IDCT/IDST architecture for HEVC standard","authors":"Ziyou Yao, Weifeng He, L. Hong, Guanghui He, Zhigang Mao","doi":"10.1109/ISCAS.2014.6865683","DOIUrl":"https://doi.org/10.1109/ISCAS.2014.6865683","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"201 1","pages":"2511-2514"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72927023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Pouros, V. Vassios, D. K. Papakostas, A. Hatzopoulos
{"title":"Input stimulus comparison using an adaptive FPGA-based testing system","authors":"S. Pouros, V. Vassios, D. K. Papakostas, A. Hatzopoulos","doi":"10.1109/ISCAS.2014.6865119","DOIUrl":"https://doi.org/10.1109/ISCAS.2014.6865119","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"93 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80535843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jelena Dragas, David Jäckel, Felix Franke, Andreas Hierlemann
{"title":"High-Throughput Hardware for Real-Time Spike Overlap Decomposition in Multi-Electrode Neuronal Recording Systems.","authors":"Jelena Dragas, David Jäckel, Felix Franke, Andreas Hierlemann","doi":"10.1109/ISCAS.2014.6865221","DOIUrl":"10.1109/ISCAS.2014.6865221","url":null,"abstract":"<p><p>Spike overlaps occur frequently in dense neuronal network recordings, creating difficulties for spike sorting. Brainmachine interfaces and <i>in vivo</i> studies of neuronal network dynamics often require that an accurate spike sorting be done in real time, with low execution latency (on the order of milliseconds). Moreover, modern neuronal recording systems that feature thousands of electrodes require processing of several tens or hundreds of neurons in parallel. The existing algorithms capable of performing spike overlap decomposition are generally very complex and unsuitable for real-time implementation, especially for an on-chip implementation. Here we present a hardware device capable of processing pair-wise spike overlaps in real time. A previously-published spike sorting algorithm, which is not suitable for processing data of large neuronal networks with low latency, has been optimized for high-throughput, low-latency hardware implementation. The designed hardware architecture has been verified on an FPGA platform. Low spike sorting error rates (0.05) for overlapping spikes have been achieved with a latency of 2.75 ms, rendering the system particularly suitable for use in closed-loop experiments.</p>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2014 ","pages":"658-661"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7612165/pdf/EMS140528.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"39789438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors","authors":"G. Salgado, G. Jovanovic-Dolecek, J. M. Rosa","doi":"10.1109/ISCAS.2013.6572082","DOIUrl":"https://doi.org/10.1109/ISCAS.2013.6572082","url":null,"abstract":"This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"252 7","pages":"1260-1263"},"PeriodicalIF":0.0,"publicationDate":"2013-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72548521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of Prior Knowledge on the Accuracy Limit of Parameter Estimation in Single-Molecule Fluorescence Microscopy.","authors":"Zhiping Lin, Yau Wong, Raimund J Ober","doi":"10.1109/ISCAS.2013.6572093","DOIUrl":"https://doi.org/10.1109/ISCAS.2013.6572093","url":null,"abstract":"In estimation theory, it is known that prior knowledge of parameters can improve the Cramér-Rao lower bound (CRLB). In this paper, we study the influence of prior knowledge on the CRLB of the estimates of the parameters that describe the trajectory of a moving object (single molecule). Since the CRLB is obtained from the inverse of the Fisher information matrix, we present a general expression of the Fisher information matrix in terms of the image function, the object trajectory and the prior knowledge matrix. Applying this expression to an object moving linearly in a two-dimensional (2D) plane with two distinct cases of prior knowledge, explicit CRLB expressions are derived. From these expressions, we show that the improvement in the CRLB of the parameter estimates is dependent on which parameters are known.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2013 ","pages":"1304-1307"},"PeriodicalIF":0.0,"publicationDate":"2013-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.2013.6572093","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"34276334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Behavioral modeling techniques for teaching communication circuits and systems","authors":"J. M. Rosa","doi":"10.1109/ISCAS.2012.6271796","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271796","url":null,"abstract":"This paper discusses the use of behavioral simulation techniques to improve the quality of teaching/learning circuits and systems for communications. The proposed pedagogical methodology has been applied in several electrical engineering courses, in both undergraduate and master degrees. The method allows students to better understand some complex circuit-and physical-level phenomena, by describing them at a higher abstraction level. In addition to enhance their understanding of design problems and skills, students become more motivated and satisfied. As an application, two case studies are considered in this work: a radio-frequency front-end system and an analog-to-digital converter. In both cases, behavioral models of the different building blocks have been implemented in MATLAB/SIMULINK and used by the students enrolled in two courses named: Electronic Circuits for Communications and Wireless Transceivers: Standards, Techniques and Architectures.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"81 1","pages":"2453-2456"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81611981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Leonardo, T. Ronald, Abt Felix, Heider Andreas, Blug Andreas, Hofler Heinrich
{"title":"Novel algorithm for the real time multi-feature detection in laser beam welding","authors":"N. Leonardo, T. Ronald, Abt Felix, Heider Andreas, Blug Andreas, Hofler Heinrich","doi":"10.1109/ISCAS.2012.6271618","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271618","url":null,"abstract":"In this paper, a novel visual multi-feature detecting algorithm for the real time monitoring and control of laser beam welding (LBW) processes is discussed. It was implemented in the Eye-RIS vision system (VS) which includes a focal plane processor programmable by typical Cellular Neural Network (CNN) operators. The algorithm is based on the extraction of “spatters” - explosions of rear melt pool - to provide on-line quality information about the process and on the detection of the full penetration hole (FPH) for the laser power control to maintain a constant penetration depth into the workpiece. A single image evaluating step is performed in about 90 µs.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"181-184"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81813691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On adaptive bounded synchronization in Power Network models","authors":"P. D. Lellis, M. Bernardo","doi":"10.1109/ISCAS.2012.6271570","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271570","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"28 1","pages":"1640-1643"},"PeriodicalIF":0.0,"publicationDate":"2012-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78908084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}