ACM Trans. Design Autom. Electr. Syst.最新文献_第8页

ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes ECDSA被动攻击、泄漏源和常见设计错误

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2820611

Jeremy Dubeuf, D. Hély, V. Beroulle

{"title":"ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes","authors":"Jeremy Dubeuf, D. Hély, V. Beroulle","doi":"10.1145/2820611","DOIUrl":"https://doi.org/10.1145/2820611","url":null,"abstract":"Elliptic Curves Cryptography (ECC) tends to replace RSA for public key cryptographic services. ECC is involved in many secure schemes such as Elliptic Curve Diffie-Hellman (ECDH) key agreement, Elliptic Curve Integrated Encryption Scheme (ECIES), and Elliptic Curve Digital Signature Algorithm (ECDSA). As for every cryptosystem, implementation of such schemes may jeopardize the inherent security provided by the mathematical properties of the ECC. Unfortunate implementation or algorithm choices may create serious vulnerabilities. The elliptic curve scalar operation is particularly sensitive among these schemes. This article surveys passive attacks against well-spread elliptic curve scalar multiplication algorithms highlighting leakage sources and common mistakes that can be used to attack the ECDSA scheme. Experimental results are provided to illustrate and demonstrate the effectiveness of each vulnerability. Finally, the article describes the link between partial leakage and lattice attack in order to understand and demonstrate the impact of small leakages on the security of ECDSA. An example of side channel and lattice attack combination on NIST P-256 is provided in the case where the elliptic curve scalar multiplication is not protected against DPA/CPA and a controllable device is not accessible.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"27 1","pages":"31:1-31:24"},"PeriodicalIF":0.0,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88752114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Parallel Power Grid Analysis Based on Enlarged Partitions 基于放大分区的并联电网分析

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2806885

Le Zhang, V. Sarin

引用次数: 2

Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements 时间规范中的辅助变量:系统级需求的语义和实际分析

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2811260

L. Pierre

引用次数: 1

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands 基于动态可重构电压-频率岛的高性价比多核soc能量优化框架

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2817207

Song Jin, Songwei Pei, Yinhe Han, Huawei Li

{"title":"A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands","authors":"Song Jin, Songwei Pei, Yinhe Han, Huawei Li","doi":"10.1145/2817207","DOIUrl":"https://doi.org/10.1145/2817207","url":null,"abstract":"Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multicore chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or required per-core voltage domain configuration. However, the former solution is hard to find one optimal VFI partition for diverse applications while the latter one suffers from high hardware cost. In this article, we propose a cost effective energy optimization framework based on dynamically reconfigurable VFI (D-VFI). Our framework treats a small number of cores as dynamic cores (D-cores) and configures each of them with an independent voltage domain. At runtime, the D-cores can be pieced together with neighboring static VFIs by scaling their operating voltages. This can dynamically construct the optimal VFI partitions for different kinds of applications, thus achieving more aggressive energy optimization under low cost. To identify the D-cores, we propose a rules constrained task scheduling and VFI partitioning algorithm. Moreover, we analyze the task schedules to determine the optimal scaling intervals which can accommodate voltage scaling induced latency. Experimental results demonstrate that the effectiveness of the proposed scheme.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"559 1","pages":"27:1-27:14"},"PeriodicalIF":0.0,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77599439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions 通过为一些自定义指令分配额外周期来改进可扩展处理器的产量和加速

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2830566

M. Kamal, A. Afzali-Kusha, S. Safari, M. Pedram

{"title":"Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions","authors":"M. Kamal, A. Afzali-Kusha, S. Safari, M. Pedram","doi":"10.1145/2830566","DOIUrl":"https://doi.org/10.1145/2830566","url":null,"abstract":"In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and extending the clock period for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication analysis, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violations are prevented, and all manufactured extensible processors will work with a predefined clock cycle time. To study the effect of the objective function (used during the CI selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps increase the speedup achieved by the extensible processor. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of approaches that do not consider the impact of process variations.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"92 1","pages":"28:1-28:25"},"PeriodicalIF":0.0,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85468991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing 一种基于单播的片上路由器组播方案及互连测试

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2821506

D. Xiang, Kele Shen

{"title":"A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing","authors":"D. Xiang, Kele Shen","doi":"10.1145/2821506","DOIUrl":"https://doi.org/10.1145/2821506","url":null,"abstract":"3D technology for networks-on-chip (NOCs) becomes attractive. It is important to present an effective scheme for 3D stacked NOC router and interconnect testing. A new approach to testing of NOC routers is proposed by classifying the routers. Routers with the same number of input/output ports fall into the same class. Routers of the same class are identical if their tests are the same. A test packet is delivered to all the identical routers by a simple unicast-based multicast scheme. It is found that the depth of the consumption buffer at each router has great impact on the test delivery time because test application and test delivery for router testing cannot be handled concurrently. Test delivery must set a router to operational mode. A mathematical model is presented to evaluate the impact of consumption buffer depth on the test delivery time. A new and simple test application scheme is proposed for interconnect testing. Some interesting extensions are presented for further test time reduction and thermal considerations. Sufficient experimental results are presented by comparison with one previous method. The proposed method works for single stuck-at, transition, even small delay faults at routers, and single bridging faults at physical, consumption and injection channels.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"144 1","pages":"24:1-24:23"},"PeriodicalIF":0.0,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76619533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis 高级综合中可靠感知的资源分配与绑定

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2016-01-28 DOI: 10.1145/2839300

Liang Chen, Mojtaba Ebrahimi, M. Tahoori

引用次数: 17

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation 基于模拟激励的数字芯片唯一id自适应生成

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2015-06-24 DOI: 10.1145/2732408

Chandra K. H. Suresh, S. Ozev, O. Sinanoglu

{"title":"Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation","authors":"Chandra K. H. Suresh, S. Ozev, O. Sinanoglu","doi":"10.1145/2732408","DOIUrl":"https://doi.org/10.1145/2732408","url":null,"abstract":"Globalization of the integrated circuit design and manufacturing flow has successfully ameliorated design complexity and fabrication cost challenges, and helped deliver cost-effective products while meeting stringent time-to-market requirements. On the flip side, it has resulted in various forms of security vulnerabilities in the supply chain that involves designers, fabs, test facilities, and distributors until the end-product reaches customers. One of the biggest threats to semiconductor industry today is the entry of aged, reject, or cloned parts, that is, counterfeit chips, into the supply chain, leading to annual revenue losses in the order of billions of dollars. While traceability of chips between trusted parties can help monitor the supply chain at various points in the flow, existing solutions are in the form of integrating costly hardware units on chip, or utilizing easy-to-circumvent inspection-based detection techniques. In this article, we propose a technique for adaptive unique ID generation that leverages process variations, enabling chip traceability. The proposed method stimulates digital chips with an analog signal from the supply lines, which serve as primary inputs to each gate in the signal path. Using a sinusoidal signal that exercises the transistors as gain components, we create a chip-specific response that can be post-processed into a digital ID. The proposed technique enables quick and cost-effective authenticity validation that requires no on-chip hardware support. Our simulation and experimentation on actual chips show that the proposed technique is capable of generating unique IDs even in the presence of environmental noise.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"32 1","pages":"46:1-46:18"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91293405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection 基于代表性关键路径选择的老化和变化感知延迟监测

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2015-06-24 DOI: 10.1145/2746237

F. Firouzi, Fangming Ye, K. Chakrabarty, M. Tahoori

引用次数: 28

Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips 在专用数字微流控生物芯片上制备可感知布局的生化液混合物

ACM Trans. Design Autom. Electr. Syst. Pub Date : 2015-06-24 DOI: 10.1145/2714562

Sudip Roy, P. Chakrabarti, Srijan Kumar, K. Chakrabarty, B. Bhattacharya

{"title":"Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips","authors":"Sudip Roy, P. Chakrabarti, Srijan Kumar, K. Chakrabarty, B. Bhattacharya","doi":"10.1145/2714562","DOIUrl":"https://doi.org/10.1145/2714562","url":null,"abstract":"The recent proliferation of digital microfluidic (DMF) biochips has enabled rapid on-chip implementation of many biochemical laboratory assays or protocols. Sample preprocessing, which includes dilution and mixing of reagents, plays an important role in the preparation of assays. The automation of sample preparation on a digital microfluidic platform often mandates the execution of a mixing algorithm, which determines a sequence of droplet mix-split steps (usually represented as a mixing graph). However, the overall cost and performance of on-chip mixture preparation not only depends on the mixing graph but also on the resource allocation and scheduling strategy, for instance, the placement of boundary reservoirs or dispensers, mixer modules, storage units, and physical design of droplet-routing pathways. In this article, we first present a new mixing algorithm based on a number-partitioning technique that determines a layout-aware mixing tree corresponding to a given target ratio of a number of fluids. The mixing graph produced by the proposed method can be implemented on a chip with a fewer number of crossovers among droplet-routing paths as well as with a reduced reservoir-to-mixer transportation distance. Second, we propose a routing-aware resource-allocation scheme that can be used to improve the performance of a given mixing algorithm on a chip layout. The design methodology is evaluated on various test cases to demonstrate its effectiveness in mixture preparation with the help of two representative mixing algorithms. Simulation results show that on average, the proposed scheme can reduce the number of crossovers among droplet-routing paths by 89.7% when used in conjunction with the new mixing algorithm, and by 75.4% when an earlier algorithm [Thies et al. 2008] is used.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"11 1","pages":"45:1-45:34"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90317294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23