ACM Transactions on Design Automation of Electronic Systems (TODAES)最新文献_第6页

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition FUBOCO:基于功能块组成的基本运算放大器结构合成

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-19 DOI: 10.1145/3522738

Inga Abel, H. Graeb

引用次数: 6

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors 具有等主输入向量的位移发射(LOS)试验下的等效故障

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-15 DOI: 10.1145/3440013

I. Pomeranz

引用次数: 0

Directed Test Generation for Activation of Security Assertions in RTL Models RTL模型中安全断言激活的定向测试生成

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-15 DOI: 10.1145/3441297

Hasini Witharana, Yangdi Lyu, P. Mishra

引用次数: 7

Machine Learning for Statistical Modeling 统计建模的机器学习

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-13 DOI: 10.1145/3440014

Urmimala Roy, T. Pramanik, Subhendu Roy, Avhishek Chatterjee, L. F. Register, S. Banerjee

{"title":"Machine Learning for Statistical Modeling","authors":"Urmimala Roy, T. Pramanik, Subhendu Roy, Avhishek Chatterjee, L. F. Register, S. Banerjee","doi":"10.1145/3440014","DOIUrl":"https://doi.org/10.1145/3440014","url":null,"abstract":"We propose a methodology to perform process variation-aware device and circuit design using fully physics-based simulations within limited computational resources, without developing a compact model. Machine learning (ML), specifically a support vector regression (SVR) model, has been used. The SVR model has been trained using a dataset of devices simulated a priori, and the accuracy of prediction by the trained SVR model has been demonstrated. To produce a switching time distribution from the trained ML model, we only had to generate the dataset to train and validate the model, which needed ∼500 hours of computation. On the other hand, if 106 samples were to be simulated using the same computation resources to generate a switching time distribution from micromagnetic simulations, it would have taken ∼250 days. Spin-transfer-torque random access memory (STTRAM) has been used to demonstrate the method. However, different physical systems may be considered, different ML models can be used for different physical systems and/or different device parameter sets, and similar ends could be achieved by training the ML model using measured device data.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"21 1","pages":"1 - 17"},"PeriodicalIF":0.0,"publicationDate":"2021-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84914690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops 基于故障的内建锁相环自检测与评估

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-08 DOI: 10.1145/3427911

Mehmet Ince, E. Yilmaz, Wei Fu, Joonsung Park, K. Nagaraj, L. Winemberg, S. Ozev

引用次数: 2

Covering Test Holes of Functional Broadside Tests 覆盖功能舷侧测试孔

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2021-01-06 DOI: 10.1145/3441282

I. Pomeranz

{"title":"Covering Test Holes of Functional Broadside Tests","authors":"I. Pomeranz","doi":"10.1145/3441282","DOIUrl":"https://doi.org/10.1145/3441282","url":null,"abstract":"Functional broadside tests were developed to avoid overtesting of delay faults. The tests achieve this goal by creating functional operation conditions during their functional capture cycles. To increase the achievable fault coverage, close-to-functional scan-based tests are allowed to deviate from functional operation conditions. This article suggests that a more comprehensive functional broadside test set can be obtained by replacing target faults that cannot be detected with faults that have similar (but not identical) detection conditions. A more comprehensive functional broadside test set has the advantage that it still maintains functional operation conditions. It covers the test holes created when target faults cannot be detected by detecting similar faults. The article considers the case where the target faults are transition faults. When a standard transition fault, with an extra delay of a single clock cycle, cannot be detected, an unspecified transition fault is used instead. An unspecified transition fault captures the behaviors of transition faults with different extra delays. When this fault cannot be detected, a stuck-at fault is used instead. A stuck-at fault has some of the detection conditions of a transition fault. Multicycle functional broadside tests are used to allow unspecified transition faults to be detected. As a by-product, test compaction also occurs. The structure of the test generation procedure accommodates the complexity of producing functional broadside tests by considering the target as well as replacement faults together. Experimental results for benchmark circuits demonstrate the fault coverage improvements achieved, and the effect on the number of tests.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"8 1","pages":"1 - 15"},"PeriodicalIF":0.0,"publicationDate":"2021-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79921384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems 节能神经形态系统的近似学习与容错映射

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-12-30 DOI: 10.1145/3436491

A. Gebregiorgis, M. Tahoori

{"title":"Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems","authors":"A. Gebregiorgis, M. Tahoori","doi":"10.1145/3436491","DOIUrl":"https://doi.org/10.1145/3436491","url":null,"abstract":"Brain-inspired deep neural networks such as Convolutional Neural Network (CNN) have shown great potential in solving difficult cognitive problems such as object recognition and classification. However, such architectures have high computational energy demand and sensitivity to variation effects, making them inapplicable for energy-constrained embedded learning platforms. To address this issue, we propose a learning and mapping approach that utilizes approximate computing during early design phases for a layer-wise pruning and fault tolerant weight mapping scheme of reliable and energy-efficient CNNs. In the proposed approach, approximate CNN is prepared first by layer-wise pruning of approximable neurons, which have high error tolerance margins using a two-level approximate learning methodology. Then, the pruned network is retrained to improve its accuracy by fine-tuning the weight values. Finally, a fault-tolerant layer-wise neural weight mapping scheme is adopted to aggressively reduce memory operating voltage when loading the weights of error resilient layers for energy-efficiency. Thus, the combination of approximate learning and fault tolerance aware memory operating voltage downscaling techniques enable us to implement robust and energy-efficient approximate inference engine for CNN applications. Simulation results show that the proposed fault tolerant and approximate learning approach can improve the energy-efficiency of CNN inference engines by more than 50% with less than 5% reduction in classification accuracy. Additionally, more than 26% energy-saving is achieved by using the proposed layer-wise mapping-based cache memory operating voltage down-scaling.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"19 1","pages":"1 - 23"},"PeriodicalIF":0.0,"publicationDate":"2020-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85337649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements 基于分析模型和测量相结合的混合评估的mpsoc映射数据流应用的多目标优化

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-12-30 DOI: 10.1145/3431814

Martín Letras, J. Falk, T. Schwarzer, Jürgen Teich

{"title":"Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements","authors":"Martín Letras, J. Falk, T. Schwarzer, Jürgen Teich","doi":"10.1145/3431814","DOIUrl":"https://doi.org/10.1145/3431814","url":null,"abstract":"Dataflow modeling is well suited for a large variety of applications for modern multi-core architectures, e.g., from the signal processing and the control domain. Furthermore, Design Space Exploration (DSE) can be used to explore mappings of tasks to hardware resources (cores of an MPSoC) and their scheduling to obtain optimized trade-off solutions between throughput and resource costs. However, the throughput evaluation of an implementation candidate via compilation-in-the-loop or simulation-based approaches can be extremely time-consuming. Such a deficiency is very detrimental, because a typical DSE run needs to evaluate thousands of implementation candidates. As a remedy, we propose a hybrid-adaptive DSE where a max-plus algebra-based analytic throughput calculation method is used in the initial DSE phase to enable a fast progress of the search space exploration. However, as this analysis may be inaccurate as neglecting some real-world effects like cache and scheduling overhead, throughput measurements are taken later in the DSE. Moreover, we explore the trade-off between scheduling efficiency of implementation candidates—in favor of reducing concurrency—and exploiting concurrency to a large extent for parallel execution of the application. To find solutions of highest achievable throughput, it is shown that not only highly scheduling efficient implementation candidates but also highly parallel implementation candidates are essential when determining the initial population. In this realm, we contribute a method for diversity-based population initialization. For a representative set of benchmarks, it is shown that the combination of the two major contributions allows us to find much higher throughput multi-core solutions within a given exploration time compared to a state-of-the-art DSE approach.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"12 1","pages":"1 - 33"},"PeriodicalIF":0.0,"publicationDate":"2020-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76696194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Logic Diagnosis with Hybrid Fail Data 混合故障数据的逻辑诊断

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-12-17 DOI: 10.1145/3433929

I. Pomeranz, M. E. Amyeen

{"title":"Logic Diagnosis with Hybrid Fail Data","authors":"I. Pomeranz, M. E. Amyeen","doi":"10.1145/3433929","DOIUrl":"https://doi.org/10.1145/3433929","url":null,"abstract":"Yield improvement requires information about the defects present in faulty units. This information is derived by applying a logic diagnosis procedure to the fail data collected by a tester from faulty units. It is typical in the early stages of yield learning to find faulty units that produce excessive volumes of fail data. The current practice is to terminate the fail data collection and possibly discard the fail data already collected for the unit. An earlier study shows that a faulty unit may produce excessive volumes of fail data for some tests but not for others. Based on this observation, a possible solution is to collect full fail data only for tests where this is feasible and pass/fail information for other tests. For this approach to be practical, it is necessary to be able to perform logic diagnosis with hybrid fail data that consists of full fail data for some tests and only pass/fail information for other tests. The main challenge in designing such a procedure is to balance the use of the two types of data to produce accurate logic diagnosis results. This article describes a logic diagnosis procedure, from the class of procedures used by commercial tools, that addresses this challenge. Experimental results for benchmark circuits demonstrate the importance of pass/fail information in this scenario.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"22 1","pages":"1 - 13"},"PeriodicalIF":0.0,"publicationDate":"2020-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80205578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization 一种鲁棒的基于模的矩阵分裂迭代混合单元高度电路合法化方法

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-12-07 DOI: 10.1145/3423326

Jianli Chen, Ziran Zhu, Wen-xing Zhu, Yao-Wen Chang

{"title":"A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization","authors":"Jianli Chen, Ziran Zhu, Wen-xing Zhu, Yao-Wen Chang","doi":"10.1145/3423326","DOIUrl":"https://doi.org/10.1145/3423326","url":null,"abstract":"Modern circuits often contain standard cells of different row heights to meet various design requirements. Taller cells give larger drive strengths and higher speed at the cost of larger areas and power. Multi-row height standard cells incur challenging issues for layout designs, especially the mixed-cell-height legalization problem with heterogeneous cell structures. Honoring the good cell positions from global placement, we present in this article a robust modulus-based matrix splitting iteration method (RMMSIM) to solve the mixed-cell-height legalization problem. Fixing the cell ordering from global placement and relaxing the right-boundary constraints, our proposed method first converts the problem into an equivalent linear complementarity problem (LCP), and then properly splits the matrices in the LCP so that the RMMSIM can solve the LCP optimally. The RMMSIM effectively explores the sparse characteristic of a circuit, and takes only linear time per iteration; as a result, it can solve the QP very efficiently. Finally, an allocation scheme for illegal cells is used to align such cells to placement sites on rows and fix the placement of out-of-right-boundary cells, if any. Experimental results show the effectiveness and efficiency of our proposed algorithm. In addition, the RMMSIM convergence and optimality are theoretically proved and empirically validated. In particular, this article provides a new RMMSIM formulation for various optimization problems that require solving large-scale convex quadratic programming problems efficiently.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"37 1","pages":"1 - 28"},"PeriodicalIF":0.0,"publicationDate":"2020-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86878341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5