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2019 Austrochip Workshop on Microelectronics (Austrochip)最新文献

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A Noise Analysis Based Design Approach of a Fully Differential Voltage Controlled Current Source for Fluxgate Sensor Excitation 基于噪声分析的全差分压控磁通门传感器励磁电流源设计方法
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00014
Maximilian Scherzer, M. Auer
{"title":"A Noise Analysis Based Design Approach of a Fully Differential Voltage Controlled Current Source for Fluxgate Sensor Excitation","authors":"Maximilian Scherzer, M. Auer","doi":"10.1109/Austrochip.2019.00014","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00014","url":null,"abstract":"Fluxgate sensors can be used in a different range of applications, where the magnetic field needs to be measured. They are known for their high dynamic range and outstanding linearity. To drive the sensor a dedicated electronic circuitry is required to retain these excellent qualities. A fully differential voltage controlled current source can be used for the linearization of the fluxgate sensor via excitation of the feedback coil. In this paper a noise analysis was accomplished for an excitation circuit which is based on an Improved Howland Current Source in bridge configuration. Further, a noise improved design approach for a spaceborne fluxgate magnetometer is presented. For this reason a Verilog-A based model of a single ended operational amplifier is employed. Simulation results with Cadence Spectre ® show a signal-to-noise ratio of 119.9 dB, if the presented design flow is used.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"80 1","pages":"10-13"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81213734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technical Program and Reviewing Committee 技术方案和评审委员会
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/austrochip.2019.00007
Austrochip, M. Auer, B. Deutschmann
{"title":"Technical Program and Reviewing Committee","authors":"Austrochip, M. Auer, B. Deutschmann","doi":"10.1109/austrochip.2019.00007","DOIUrl":"https://doi.org/10.1109/austrochip.2019.00007","url":null,"abstract":"Mario Auer, Institute of Electronics, Graz University of Technology, Austria Alexander Bergmann, Institute of Electronic Sensor Systems, Graz University of Technology, Austria Bernd Deutschmann, Institute of Electronics, Graz University of Technology, Austria Dieter Draxelmayr, Infineon Technologies Austria, Austria Martin Horauer, Research Group Embedded Systems, University of Applied Sciences Technikum Wien, Austria Mario Huemer, Institute of Signal Processing, Johannes Kepler University Linz, Austria Michael Hutter, Rambus Technologies, USA Nikolaus Keroe, Oregano Systems, Austria Hans-Peter Kreuter, Infineon Technologies Austria, Austria Manfred Ley, Carinthia University of Applied Sciences, Villach, Austria Christian Netzberger, FH Joanneum, University of Applied Sciences, Kapfenberg, Austria Burkhard Neurauter, eesy-ic, Austria Timm Ostermann, Institute for Integrated Circuits, Johannes Kepler University Linz, Austria Harald Pretl, Institute for Integrated Circuits, Johannes Kepler University Linz, Austria Peter Roessler, Research Group Embedded Systems, University of Applied Sciences Technikum Wien, Austria Gregor Schatzberger, ams AG, Austria Kerstin Schneider-Hornstein, Institute of Electrodynamics, Microwave & Circuit Engineering, Vienna University of Technology, Austria Peter Soeser, Institute of Electronics, Graz University of Technology, Austria Andreas Steininger, Institute of Computer Engineering, Vienna University of Technology, Austria Johannes Sturm, Carinthia University of Applied Sciences, Villach, Austria Gunter Winkler, Institute of Electronics, Graz University of Technology, Austria Johannes Wolkerstorfer, xFace, Graz, Austria Horst Zimmermann, Institute of Electrodynamics, Microwave & Circuit Engineering, Vienna University of Technology, Austria","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89260977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Systematic Approach to Clock Failure Detection 时钟故障检测的系统方法
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00018
A. Steininger, Martin Schwendinger
{"title":"A Systematic Approach to Clock Failure Detection","authors":"A. Steininger, Martin Schwendinger","doi":"10.1109/Austrochip.2019.00018","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00018","url":null,"abstract":"Many of today's chips comprise multiple clock domains and some even have multiple clock sources. This makes supervision of the correct operation of a clock increasingly important. Rather than promoting a specific approach for clock failure detection, this paper tries to provide a systematic overview of the available options. To this end, requirements and principles are identified and discussed first, and then related implementations are shown. These are partly revisiting existing solutions from the literature that are put into the context, and partly constituting novel solutions. The implementations are evaluated according to several criteria, like detection latency, implementation efforts, and, most notably, potential for metastability issues. The purpose of the paper is to give the designer a guideline, showing which techniques are available, along with a critical assessment that shall help in making the appropriate choice for a given application.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"15 1","pages":"35-42"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79425646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of a Cost-Efficient Passive Visible Light Sensing Approach for the Determination of Surface Colors 一种具有成本效益的表面颜色测定被动可见光传感方法的实现
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00026
A. Weiss, Kushal Madane, Saman Zahiri Rad, F. Wenzl
{"title":"Implementation of a Cost-Efficient Passive Visible Light Sensing Approach for the Determination of Surface Colors","authors":"A. Weiss, Kushal Madane, Saman Zahiri Rad, F. Wenzl","doi":"10.1109/Austrochip.2019.00026","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00026","url":null,"abstract":"After the successful penetration of light-emitting diodes (LEDs) into the lighting market in the past, nowadays functionalities beyond illumination become more and more of relevance. Recent attempts in this regard focus on communication, localization and most recently also on sensing with light. In this paper, we demonstrate a simple and costeffective approach to identify different surface colors exemplarily shown on a differently colored cube as a passive object and an LED and an RGB sensitive photodiode as emitter and receiver in a visible light sensing setup. We introduce an algorithm, which after successive characterization, measurement and decision-making steps allows the determination of the individual surface colors by an RGB photodiode with high accuracy. We also present a simple correction procedure, which allows maintaining the accuracy in color identification without the need to repeat the timeconsuming characterization step for any change in the lighting conditions. This approach could become part of future visible light communication, positioning and sensing networks, which, besides exchanging information, also detect incidents in their surroundings.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"117 1","pages":"81-86"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77147796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Open-Source Crypto IP Cores for FPGAs – Overview and Evaluation fpga的开源加密IP核-概述和评估
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00020
M. Billmann, S. Werner, Roland Holler, Friedrich Praus, Andreas Puhm, N. Kero
{"title":"Open-Source Crypto IP Cores for FPGAs – Overview and Evaluation","authors":"M. Billmann, S. Werner, Roland Holler, Friedrich Praus, Andreas Puhm, N. Kero","doi":"10.1109/Austrochip.2019.00020","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00020","url":null,"abstract":"With the increasing number of electronic based systems being connected to the Internet via wired or wireless connections in the era of the IoT, the importance of security aspects is well recognized. At the same time growth of available complexity and increasing market share of reconfigurable integrated circuits make integration of whole digital systems feasible at relatively low cost. Placing security functions into reconfigurable logic might be advantageous in case of algorithm changes, bug fixes, or updates for hardening of the core against attacks. In this paper we thus want to give an overview of available open-source hardware security building blocks for basic cryptographic functions and show evaluation results of selected cores in FPGA technology.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"106 1","pages":"47-54"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81119269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Time-Domain Temperature Sensor using Nwell Diodes on 820µm^2 in 7nm FinFET 采用Nwell二极管820µm^2 in 7nm FinFET的时域温度传感器
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00013
M. Eberlein, H. Pretl, Tim Krebs
{"title":"A Time-Domain Temperature Sensor using Nwell Diodes on 820µm^2 in 7nm FinFET","authors":"M. Eberlein, H. Pretl, Tim Krebs","doi":"10.1109/Austrochip.2019.00013","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00013","url":null,"abstract":"We present a novel concept for thermal sensing, which provides a duty-cycle modulated output signal for high resolution measurement. The circuit is self-contained and features distinct simplicity, containing only a few switches, capacitors and an auto-zero comparator. The active Nwell-Substrate diode is utilized as a robust sensing device in advanced FinFET nodes. Two sampling capacitors operate as a charge-pump and discharge periodically across the diode. The sampled voltages represent PTAT and CTAT signals, which are balanced by means of adjusting the diode current through pulse timings. This control pulses are generated in a feedback loop by the comparator and a counter, while the temperature is extracted from their duty-cycle. Our prototype in 7nm FinFET consumes only 820µm2 active area, due to low matching requirements. From simulated data, the sensor operates down to Vdd = 0.90V and achieves an untrimmed accuracy of ±2.8°C from -10°C to 120°C. It dissipates ~11µW including an internal clock generator, with a conversion time between 2.5µs and 600µs.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"6 1","pages":"6-9"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79068887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Matching Considerations for Bidirectional Current Mirrors 双向电流镜的匹配考虑
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00023
I. Siegl, Markus Haberler, C. Steffan
{"title":"Matching Considerations for Bidirectional Current Mirrors","authors":"I. Siegl, Markus Haberler, C. Steffan","doi":"10.1109/Austrochip.2019.00023","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00023","url":null,"abstract":"This paper elaborates in detail which matching dynamics occur when mirroring bidirectional currents. Formulas for the matching error of bidirectional current mirrors are deduced from the unidirectional case. Simulation results confirm these calculations and verify that the matching degradation due to the bidirectional nature is stronger than the degradation due to the transistor coming into weak inversion. Depending on whether or not calibration is acceptable the paper states suitable design considerations.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"1 1","pages":"65-70"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88910927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Single-to-Differential Transimpedance Amplifier for Low-Noise and High-Speed Optical Receivers 用于低噪声和高速光接收机的单对差分跨阻放大器
2019 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2019-10-01 DOI: 10.1109/Austrochip.2019.00025
B. Mesgari, H. Mahmoudi, H. Zimmermann
{"title":"A Single-to-Differential Transimpedance Amplifier for Low-Noise and High-Speed Optical Receivers","authors":"B. Mesgari, H. Mahmoudi, H. Zimmermann","doi":"10.1109/Austrochip.2019.00025","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00025","url":null,"abstract":"This paper presents a transimpedance amplifier (TIA) topology to realize single-ended to differential conversion with no need for a dummy amplifier. The proposed structure includes a Common-Gate Common-Source (CG-CS) topology incorporating an input impedance modification path which allows a large photodiode capacitance. Accordingly, the TIA is designed in 0.35-µm CMOS technology and post-layout simulations show that the circuit can be used in wideband optical communication systems. Consuming 10mW from a 3.3 V supply, the circuit has 2.25 GHz bandwidth and 56.1 dB gain rendering possible a 400 fF capacitance at the input node of the TIA. The input-referred noise of the circuit is lower than 15.5 pA/√Hz and the integrated input noise current is less than 0.6 µA. The TIA demonstrates a gain and phase imbalance of less than 1.5 dB and 5 degrees respectively in the entire bandwidth of interest.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"6 1","pages":"76-80"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80363586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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