2015 IEEE Hot Chips 27 Symposium (HCS)最新文献_第2页

Silicon Radiation Detector Technologies: From Planar to 3D 硅辐射探测器技术:从平面到三维

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-04-13 DOI: 10.3390/chips2020006

G. Dalla Betta, Jixing Ye

引用次数: 3

Approximate Content-Addressable Memories: A Review 近似内容可寻址存储器:综述

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-03-30 DOI: 10.3390/chips2020005

Esteban Garzón, L. Yavits, A. Teman, M. Lanuzza

引用次数: 1

Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Defined Radio 带通σ - δ调制:软件无线电中射频到数字转换的路径

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-03-02 DOI: 10.3390/chips2010004

J. M. de la Rosa

引用次数: 0

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm 采用分路电容失配补偿和动态元件匹配算法的低功耗低电路面积15位SAR ADC方法

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-02-27 DOI: 10.3390/chips2010003

William Bontems, D. Dzahini

引用次数: 0

An Interface Platform for Robotic Neuromorphic Systems 机器人神经形态系统接口平台

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-02-01 DOI: 10.3390/chips2010002

Nicola Russo, Haochun Huang, E. Donati, Thomas Madsen, K. Nikolic

引用次数: 3

Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers 基于混合逆变器的全差分跨导运算放大器

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-01-06 DOI: 10.3390/chips2010001

Luís Henrique Rodovalho, P. Toledo, F. Mir, Farshad Ebrahimi

引用次数: 2

A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology 基于改进2T拓扑的输出倍压CMOS电压基准电路

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2022-12-15 DOI: 10.3390/chips1030015

Junyao Li, P. K. Chan

{"title":"A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology","authors":"Junyao Li, P. K. Chan","doi":"10.3390/chips1030015","DOIUrl":"https://doi.org/10.3390/chips1030015","url":null,"abstract":"This paper presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable of generating higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40 nm CMOS technology, the proposed circuit operates at a minimum supply of 0.65 V and consumes 5.5 nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal Vref is 489.6 mV (75.3% of Vddmin) for the temperature range from −20 °C to 80 °C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488 mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of −45.5 dB and −76.3 dB at 100 kHz and 100 MHz. Compared to the representative prior-art works realized in the same technology and a similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output, Vref.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"13 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76078073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA Prototyping of Web Service Using REST and SOAP Packages 使用REST和SOAP包的Web服务的FPGA原型

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2022-12-05 DOI: 10.3390/chips1030014

Chee Er Chang, A. K. Mustapha, F. Mohd-Yasin

引用次数: 0

Multi-Physics Fields Simulations and Optimization of Solder Joints in Advanced Electronic Packaging 先进电子封装中焊点的多物理场模拟与优化

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2022-11-17 DOI: 10.3390/chips1030013

Boyan Yu, Yi Gao

引用次数: 0

An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement 基于fpga的时间测量改进自适应下采样TDC实现

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2022-11-08 DOI: 10.3390/chips1030012

Evangelos Dikopoulos, M. Birbas, A. Birbas

{"title":"An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement","authors":"Evangelos Dikopoulos, M. Birbas, A. Birbas","doi":"10.3390/chips1030012","DOIUrl":"https://doi.org/10.3390/chips1030012","url":null,"abstract":"In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant issues regarding delay lines in FPGA-based TDCs, combined with the fact that delay lines are utilized for a wide range of TDC architectures (not limited to the delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also in different FPGA devices, can directly benefit from the proposed adaptive method, with no need for either custom routing or complex tuning of the converter. Furthermore, implementation-related challenges regarding clock skew, measurement uncertainty, and the placement of the TDC are discussed and we also propose an experimental setup that utilizes only FPGA resources in order to characterize the converter. Although the TDC in this work was implemented in a Xilinx Virtex-6 device and was characterized under different operational modes, we successfully optimized the converter’s nonlinearity and resource utilization while retaining single-shot precision. The best performing (in terms of linearity) implementation reached DNLrms and INLrms values of 0.30 LSB and 0.45 LSB, respectively, and the single-shot precision (σ) was 9.0 ps.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"41 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90495860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2