2015 IEEE Hot Chips 27 Symposium (HCS)最新文献

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison 赢家通吃和输家通吃电路:架构、应用和分析比较

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-11-08 DOI: 10.3390/chips2040016

Ehsan Rahiminejad, Hamed Aminzadeh

引用次数: 0

A Survey of Automotive Radar and Lidar Signal Processing and Architectures 汽车雷达和激光雷达信号处理与体系结构综述

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-10-08 DOI: 10.3390/chips2040015

Luigi Giuffrida, Guido Masera, Maurizio Martina

引用次数: 0

Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search 面向5G小区搜索的3GPP物理层硬件实现设计与性能分析

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-10-07 DOI: 10.3390/chips2040014

Khalid Lodhi, Jayant Chhillar, Sumit J. Darak, Divisha Sharma

{"title":"Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search","authors":"Khalid Lodhi, Jayant Chhillar, Sumit J. Darak, Divisha Sharma","doi":"10.3390/chips2040014","DOIUrl":"https://doi.org/10.3390/chips2040014","url":null,"abstract":"5G Cell Search (CS) is the first step for user equipment (UE) to initiate communication with the 5G node B (gNB) every time it is powered ON. In cellular networks, CS is accomplished via synchronization signals (SS) broadcasted by gNB. 5G 3rd generation partnership project (3GPP) specifications offer a detailed discussion on the SS generation at gNB, but a limited understanding of their blind search and detection is available. Unlike 4G, 5G SS may not be transmitted at the center of carrier frequency, and their frequency location is unknown to UE. In this work, we demonstrate the 5G CS by designing 3GPP compatible hardware realization of the physical layer (PHY) of the gNB transmitter and UE receiver. The proposed SS detection explores a novel down-sampling approach resulting in a 60% reduction in on-chip memory and 50% lower search time. Via detailed performance analysis, we analyze the functional correctness, computational complexity, and latency of the proposed approach for different word lengths, signal-to-noise ratio (SNR), and down-sampling factors. We demonstrate end-to-end 5G CS using GNU Radio-based RFNoC framework on the USRP-FPGA platform and achieve 66% faster SS search compared to software. The 3GPP compatibility and demonstration on hardware strengthen the commercial significance of the proposed work.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135301084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Silicon Carbide: Physics, Manufacturing, and Its Role in Large-Scale Vehicle Electrification 碳化硅:物理、制造及其在大规模汽车电气化中的作用

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-09-13 DOI: 10.3390/chips2030013

Filippo Di Giovanni

{"title":"Silicon Carbide: Physics, Manufacturing, and Its Role in Large-Scale Vehicle Electrification","authors":"Filippo Di Giovanni","doi":"10.3390/chips2030013","DOIUrl":"https://doi.org/10.3390/chips2030013","url":null,"abstract":"Silicon carbide is changing power electronics; it is enabling massive car electrification owing to its far more efficient operation with respect to mainstream silicon in a large variety of energy conversion systems like the main traction inverter of an electric vehicle (EV). Its superior performance depends upon unique properties such as lower switching and conduction losses, safer high-temperature operation and high-voltage capability. Starting briefly with a description of its physics, more detailed information is then given about some key manufacturing steps such as crystal growth and epitaxy. Afterwards, an overview of its inherent defects and how to mitigate them is presented. Finally, a typical EV’s propulsion inverter is shown, proving the technology’s effectiveness in meeting requirements for mass electrification. Foreword: In recent years, SiC has drawn the attention of a growing number of power electronics designers as the material has good prospects for reducing environmental impacts on a global basis. The goal of this paper, based on the author’s contribution to the introduction of the technology at STMicroelectronics, is to show the potential of silicon carbide in enabling massive car electrification. The company’s SiC MOSFETs, tailored to the automotive industry, are enabling visionary EV makers to pave the way for sustainable e-mobility. The intent of this paper is to describe, for a large crowd of readers, how SiC features can accelerate such a transition by quantifying the benefits they bring in terms of improved efficiency in an EV electric powertrain. The paper also has the ambition to highlight the material’s physics and to give an overview of its production processes, starting from the crystal growth for realizing substrates to the main epitaxy techniques. Some space has been devoted to the analysis of the main crystal defects not present in silicon and whose nature poses new challenges in terms of manufacturing yields and screening. Finally, some insights into the market evolution and on the transition to 200 mm wafers are given.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135740455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation 利用覆盖引导模糊和联合仿真的虚拟样机辅助跨层方法对硬件外设进行协同验证

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-09-08 DOI: 10.3390/chips2030012

Sallar Ahmadi-Pour, Mathis Logemann, V. Herdt, Rolf Drechsler

{"title":"Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation","authors":"Sallar Ahmadi-Pour, Mathis Logemann, V. Herdt, Rolf Drechsler","doi":"10.3390/chips2030012","DOIUrl":"https://doi.org/10.3390/chips2030012","url":null,"abstract":"In this paper, we propose a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. In particular, we combine two approaches that complement each other and use the VP as a readily available reference model: We use (A) Coverage-Guided Fuzzing (CGF) which enables comprehensive verification at the unit-level of the Register-Transfer Level (RTL) HW peripheral with a Transaction Level Modeling (TLM) reference, and (B) an application-driven co-simulation-based approach that enables verification of the HW peripheral at the system-level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract TLM PLIC implementation from the open source RISC-V VP as the reference model. In our experiments we find three behavioral mismatches and discuss the observation of these, as well as non-functional timing behavior mismatches, that were found through the proposed synergistic approach. Furthermore, we provide a discussion and considerations on the RTL/TLM Transactors, as they embody one keystone in cross-level methods. As the different approaches uncover different mismatches in our case-study (e.g., behavioral mismatches and timing mismatches), we conclude a synergy between the methods to aid in verification efforts.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"54 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85715060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons 超低电压应用的标准电池比较器:分析和比较

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-08-18 DOI: 10.3390/chips2030011

Riccardo Della Sala, F. Centurelli, G. Scotti, G. Palumbo

{"title":"Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons","authors":"Riccardo Della Sala, F. Centurelli, G. Scotti, G. Palumbo","doi":"10.3390/chips2030011","DOIUrl":"https://doi.org/10.3390/chips2030011","url":null,"abstract":"This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"86 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89749116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier 基于近似乘法器的深度可分离卷积神经网络推理芯片设计

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-07-19 DOI: 10.3390/chips2030010

Jin-Jia Shang, Nicholas Phipps, I-Chyn Wey, T. Teo

引用次数: 0

On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities 具有自x能力的神经形态脉冲传感系统的片上自适应实现

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-06-06 DOI: 10.3390/chips2020009

H. Abd, A. König

{"title":"On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities","authors":"H. Abd, A. König","doi":"10.3390/chips2020009","DOIUrl":"https://doi.org/10.3390/chips2020009","url":null,"abstract":"In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"48 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84081478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Quantitative Review of Automated Neural Search and On-Device Learning for Tiny Devices 微型设备的自动神经搜索和设备上学习的定量综述

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-05-09 DOI: 10.3390/chips2020008

Danilo Pietro Pau, Prem Kumar Ambrose, Fabrizio Maria Aymone

引用次数: 0

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation 具有自x属性的可配置模拟前端的低成本间接测量节能现场优化:硬件实现

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2023-05-01 DOI: 10.3390/chips2020007

Q. Zaman, S. Alraho, A. König

{"title":"Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation","authors":"Q. Zaman, S. Alraho, A. König","doi":"10.3390/chips2020007","DOIUrl":"https://doi.org/10.3390/chips2020007","url":null,"abstract":"This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"13 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81592534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1