A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology

Abstract

This paper presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable of generating higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40 nm CMOS technology, the proposed circuit operates at a minimum supply of 0.65 V and consumes 5.5 nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal Vref is 489.6 mV (75.3% of  Vddmin) for the temperature range from −20 °C to 80 °C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488 mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of −45.5 dB and −76.3 dB at 100 kHz and 100 MHz. Compared to the representative prior-art works realized in the same technology and a similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output, Vref.