2018 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第4页

Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors 用于深度学习处理器的高效固定/浮点合并混合精度乘累加单元

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351354

H. Zhang, Hyuk-Jae Lee, S. Ko

{"title":"Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors","authors":"H. Zhang, Hyuk-Jae Lee, S. Ko","doi":"10.1109/ISCAS.2018.8351354","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351354","url":null,"abstract":"Deep learning is getting more and more attentions in recent years. Many hardware architectures have been proposed for efficient implementation of deep neural network. The arithmetic unit, as a core processing part of the hardware architecture, can determine the functionality of the whole architecture. In this paper, an efficient fixed/floating-point merged multiply-accumulate unit for deep learning processor is proposed. The proposed architecture supports 16-bit half-precision floating-point multiplication with 32-bit single-precision accumulation for training operations of deep learning algorithm. In addition, within the same hardware, the proposed architecture also supports two parallel 8-bit fixed-point multiplications and accumulating the products to 32-bit fixed-point number. This will enable higher throughput for inference operations of deep learning algorithms. Compared to a half-precision multiply-accumulate unit (accumulating to single-precision), the proposed architecture has only 4.6% area overhead. With the proposed multiply-accumulate unit, the deep learning processor can support both training and high-throughput inference.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"62 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83146641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A Systematic Method for Approximate Circuit Design Using Feature Selection 基于特征选择的系统近似电路设计方法

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351167

Ling Qiu, Yingjie Lao

引用次数: 4

The EcoChip: A Wireless Multi-Sensor Platform for Comprehensive Environmental Monitoring EcoChip:用于综合环境监测的无线多传感器平台

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351654

M. Sylvain, Francis Lehoux, S. Morency, Felix Faucher, E. Bharucha, D. Tremblay, Denis Sarrazin, Sylvain Moineau, Michel Allard, Jacques Corbeil, Younès Messaddeq, Benoit Gosselin

{"title":"The EcoChip: A Wireless Multi-Sensor Platform for Comprehensive Environmental Monitoring","authors":"M. Sylvain, Francis Lehoux, S. Morency, Felix Faucher, E. Bharucha, D. Tremblay, Denis Sarrazin, Sylvain Moineau, Michel Allard, Jacques Corbeil, Younès Messaddeq, Benoit Gosselin","doi":"10.1109/ISCAS.2018.8351654","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351654","url":null,"abstract":"This paper presents a new autonomous wireless sensor platform intended for the monitoring of microorganisms and molecules found in harsh environments, like in the northern climates. The EcoChip includes a layered multiwell plate that allows the growth of single strain microorganisms, within a well of the plate, isolated from environmental samples from Northern habitats. It can be deployed in the field for continuous monitoring of microbiological growth within 96 individual wells through a multichannel electro-chemical impedance monitoring circuit. Additional sensors are provided for monitoring luminosity, humidity, temperature, pH, and CO2 release. The embedded electronic board is equipped with a flash memory to accumulate and store sensor data for long periods of time, as well as with a low-power micro-controller, and a power management unit to control and supply all electronic building blocks. When a receiver is located within the transmission range of the EcoChip, a low-power wireless transceiver allows transmission of sensor data stored from on-board memory. We report the measured performance of the system, and we present experimental results obtained in the field during a pilot study performed with the EcoChip deployed in the village of Kuujjuarapik, at a latitude of 55 degrees, in Northern Canada.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"26 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83525344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Spatio-temporal compressed sensing for real-time wireless EEG monitoring 实时无线脑电图监测的时空压缩感知

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351863

Bathiya Senevirathna, P. Abshire

{"title":"Spatio-temporal compressed sensing for real-time wireless EEG monitoring","authors":"Bathiya Senevirathna, P. Abshire","doi":"10.1109/ISCAS.2018.8351863","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351863","url":null,"abstract":"Wearable electronics capable of recording and transmitting biosignals can provide convenient and pervasive health monitoring. The wireless transmission bandwidth limits the number of recording sites that can be monitored at one time. Compressed sensing (CS) is a promising approach that uses computationally efficient encoding to reduce the number of samples that are transmitted wirelessly, allowing more channels to be monitored over a transmission channel. The rakeness CS approach shows improved performance for higher compression rates, but in prior work it has only been evaluated for single channel data. We analyze the fidelity tradeoffs for compressed sensing implemented on a mobile electroencephalography (EEG) system. We propose several methods for spatiotemporal encoding in rakeness CS and evaluate the performance using a spontaneous EEG dataset recorded during moderate movement. Reconstruction performance depends strongly on the compression ratio and weakly on the method of spatiotemporal encoding. This suggests weak spatial correlation between the different channels of EEG data, which were recorded in an experiment involving self-initiated movement.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"124 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88604860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator? 我应该为我的连续时间δ - σ调制器选择什么结构?

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351141

S. Pavan, Siddharth Baskaran

引用次数: 0

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis 基于高级综合的低延迟40gb /s流量管理器设计

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351332

Imad Benacer, F. Boyer, Y. Savaria

引用次数: 3

A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient 一种新的基于NOR闪存阵列的高计算速度和高能效的卷积计算范式

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351030

Runze Han, P. Huang, Y. Xiang, C. Liu, Zhen Dong, Z. Su, Y. B. Liu, L. Liu, X. Liu, Jinfeng Kang

引用次数: 7

An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector 具有超低功耗可重构电源-复位式电压检测器的室内太阳能采集器

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351096

Xiaodong Meng, Xing Li, Y. Yao, C. Tsui, W. Ki

引用次数: 7

Drift-Invariant Detection for Multilevel Phase-Change Memory 多电平相变存储器的漂移不变检测

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351740

M. Stanisavljevic, T. Mittelholzer, N. Papandreou, Thomas Parnell, H. Pozidis

{"title":"Drift-Invariant Detection for Multilevel Phase-Change Memory","authors":"M. Stanisavljevic, T. Mittelholzer, N. Papandreou, Thomas Parnell, H. Pozidis","doi":"10.1109/ISCAS.2018.8351740","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351740","url":null,"abstract":"Next-generation memory (NGM) technologies present a major opportunity but also a significant challenge, due to their intricate reliability issues. In particular, multilevel-cell (MLC) storage is highly desirable for increasing storage capacity and lowering total cost-per-bit. In phase-change memory (PCM), MLC storage is hampered by sensitivity to temperature variations and resistance drift. A novel drift-invariant detection (DID) scheme that estimates variable read thresholds based on ordered statistics and clustering of the soft read-back signals from a small block of 32 cells has been developed and implemented in hardware to improve reliability and prolong data retention. A low-complexity implementation of the DID on a FPGA platform comprises 20'000 LUTs and 6'000 flip-flops and has a latency of 90ns. We present results from an extensive performance verification that ascertains highly reliable data retrieval up to 13 orders of magnitude in time after programming. Such elevated reliability is necessary for the most anticipated application of NGM, namely persistent far-memory, where the NGM is used as a large memory pool, possibly together with DRAM.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89529773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics 基于可重构加速器的异构集群节能近传感器数据分析

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351749

Satyajit Das, Kevin J. M. Martin, P. Coussy, D. Rossi

{"title":"A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics","authors":"Satyajit Das, Kevin J. M. Martin, P. Coussy, D. Rossi","doi":"10.1109/ISCAS.2018.8351749","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351749","url":null,"abstract":"IoT end-nodes require high performance and extreme energy efficiency to cope with complex near-sensor data analytics algorithms. Processing on multiple programmable processors operating in near-threshold is emerging as a promising solution to exploit the energy boost given by low-voltage operation, while recovering the related frequency degradation with parallelism. In this work, we present a heterogeneous cluster architecture extending a traditional parallel processor cluster with a reconfigurable Integrated Programmable Array (IPA) accelerator. While programmable processors guarantee programming legacy to easily manage peripherals, radio software stacks as well as the global program flow, offloading data-intensive and control-intensive kernels to the IPA leads to much higher system level performance and energy-efficiency. Experimental results show that the proposed heterogeneous cluster outperforms an 8-core homogeneous architecture by up to 4.8× in performance and 4.5× in energy efficiency when executing a mix of control-intensive and data-intensive kernels typical of near-sensor data analytics applications.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"35 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90267124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11