2018 IEEE 68th Electronic Components and Technology Conference (ECTC)最新文献_第6页

Effects of the Interlayer Thickness and Alloying on the Reliability of Transient Liquid Phase (TLP) Bonding 层间厚度和合金化对瞬态液相(TLP)结合可靠性的影响

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00087

Junghyun Cho, F. Dong, L. Yin, D. Shaddock

{"title":"Effects of the Interlayer Thickness and Alloying on the Reliability of Transient Liquid Phase (TLP) Bonding","authors":"Junghyun Cho, F. Dong, L. Yin, D. Shaddock","doi":"10.1109/ECTC.2018.00087","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00087","url":null,"abstract":"In an effort to replace Pb-based solders commonly used in high-temperature electronics (operating at 200°C or higher) with a new high-temperature capable material, we have developed a transient liquid phase (TLP) bonding between bismuth (Bi) and nickel (Ni) in our previous study. To address the reliability concerns and also to warrant the manufacturing efficiency of the TLP bonds, the current study was focused on the optimization of the interlayer structure and alloying via: i) thin bond-line-thickness (BLT) (< 10 um), ii) intermediate BLT (20-40 um), and iii) thick BLT (> 60 um). These TLP bonded coupons were then tested for bonding reaction, microstructure development, and mechanical reliability. A thin BLT was made via sputter deposition of Bi on Ni-metallized die, which enabled a Ni layer (? 1 um) remaining during reflow without being completely consumed. The intermediate BLT sample was made using a Bi preform as in our previous study. For the thick BLT case, a powder/paste of Bi-xNi (from x=0 to 21.9 wt.%) was used. In particular, as pure Bi will not react with the Cu metallized surface (or Cu substrate), an interlayer consisting of Bi-Ni mixed powder/paste will enable Cu surface to be bondable with this TLP system. In this paper, the reflow conditions and the interlayer microstructures for the Bi-Ni TLP bonding with the three different approaches are discussed.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"551-556"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82661626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Back-end-of-Line (BEOL) Mechanical Integrity Evaluation: A Mixed-Mode Double Cantilever Beam Test for Crackstop Strength Assessment 后端线(BEOL)机械完整性评估:用于止裂强度评估的混合模式双悬臂梁试验

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00075

Max Cioban, Tuhin Sinha, T. Shaw

{"title":"Back-end-of-Line (BEOL) Mechanical Integrity Evaluation: A Mixed-Mode Double Cantilever Beam Test for Crackstop Strength Assessment","authors":"Max Cioban, Tuhin Sinha, T. Shaw","doi":"10.1109/ECTC.2018.00075","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00075","url":null,"abstract":"Crackstops are vital parts of the back-end-of-line (BEOL) chip stack in electronic packages and are often responsible for preventing catastrophic mechanical and electrical breakdown within a semiconductor device. The present work is focused on evaluating the fracture toughness of crack-stops using a mixed-mode bending test structure. The test fixture designed as part of this study enables crack propagation in the BEOL under a wide range of mode-mixities which mimics the stress drivers within an organic flip-chip package. Techniques for optimized sample preparation beginning with a processed wafer to the final, test-ready coupon for mixed-mode testing will be discussed. The designed sample preparation tools and methods allow for the precise driving of a crack to specific features within the BEOL. Rigorous analytical verifications were conducted to validate the results obtained from the tests and it will be demonstrated that the test is highly effective for understanding the factors that can influence the strength of a crackstop and the mechanics of its strength degradation under prolonged moisture exposure.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"467-475"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82752029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design Considerations of a Matching Circuit for Low Power Wake-Up Receivers 低功率唤醒接收机匹配电路的设计考虑

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00351

J. Ou

引用次数: 0

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration 面向异构集成的芯片优先扇出面板级封装

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00061

C. Ko, Henry Yang, J. Lau, Ming Li, Margie Li, Curry Lin, JW Lin, Tony Chen, Iris Xu, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Q. Yong, N. Fan, E. Kuah, Zhang Li, K. Tan, Y. Cheung, Eric Ng, Wu Kai, J. Hao, R. Beica, M. Lin, Y. Chen, Zhong Cheng, Koh Sau Wee, Jiang Ran, Cao Xi, S. Lim, Nc Lee, Mian Tao, J. Lo, Ricky S. W. Lee

引用次数: 25

Small Shielded Bluetooth Module Equipped with Slot Antenna on the Surface 表面带有槽式天线的小型屏蔽蓝牙模块

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00036

K. Yamada, M. Sano, M. Higaki, A. Happoya

引用次数: 2

Solely Calcine Controlled Ferroelectricity and Resistivity of Barium Titanate Thin Films and Their Advanced Memory Applications 钛酸钡薄膜的完全煅烧控制铁电性和电阻率及其在高级存储器中的应用

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00214

T. Schumann, Xiaochen Zhu, J. Neff, A. Hebard, H. Zmuda, Y. Yoon

引用次数: 1

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond 利用SOI上的硅通孔实现400 Gbps及以上应用的硅光子学器件高速光互连的3D封装系统

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00129

Do-won Kim, Hong Yu Li, K. Chang, W. Loh, S. Chong, H. Cai, B. Surya

引用次数: 3

Prediction of Statistical Distribution of Vibration-Induced Solder Fatigue Failure Considering Intrinsic Variations of Mechanical Properties of Anisotropic Sn-Rich Solder Alloys 考虑各向异性富锡钎料合金力学性能内在变化的振动诱发焊料疲劳失效统计分布预测

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00115

Hsiu-Ping Wei, Yu-Hsiang Yang, Bulong Wu, B. Han

引用次数: 3

"Hole-in-One TSV", a New Via Last Concept for High Density 3D-SOC Interconnects “一杆入洞TSV”，高密度3D-SOC互连的新概念

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00228

J. de Vos, S. Van Huylenbroeck, A. Jourdain, N. Heylen, Lan Peng, G. Jamieson, N. Tutunjyan, S. Sardo, Andy Miller, E. Beyne

引用次数: 13

Interconnection Process Using Laser and Hybrid Underfill for LED Array Module on PET Substrate PET基板上LED阵列模组的激光与混合衬底互连工艺

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI: 10.1109/ECTC.2018.00238

Kwang-Seong Choi, Wagno Alves Braganca Junior, leeseul Jeong, Keon‐Soo Jang, Seok-Hwan Moon, Hyun-Cheol Bae, Y. Eom, Min-Kyo Cho, S. I. Chang

引用次数: 12