Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

2018 IEEE 68th Electronic Components and Technology Conference (ECTC) Pub Date : 2018-05-01 DOI:10.1109/ECTC.2018.00061

C. Ko, Henry Yang, J. Lau, Ming Li, Margie Li, Curry Lin, JW Lin, Tony Chen, Iris Xu, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Q. Yong, N. Fan, E. Kuah, Zhang Li, K. Tan, Y. Cheung, Eric Ng, Wu Kai, J. Hao, R. Beica, M. Lin, Y. Chen, Zhong Cheng, Koh Sau Wee, Jiang Ran, Cao Xi, S. Lim, Nc Lee, Mian Tao, J. Lo, Ricky S. W. Lee

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引用次数: 25

Abstract

The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed.

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面向异构集成的芯片优先扇出面板级封装

本研究探讨了一种由4个芯片和4个电容器组成的FOPLP(扇出面板级封装)异质集成的设计、材料、工艺、制造和可靠性。重点是应用一种称为Uni-SIP (Uni-substrate-integrated-package)的特殊组装工艺来制造FOPLP的rdl (redistribution layers)。ABF (Ajinomoto积聚膜)用作rdl的介电介质，并通过SAP(半添加工艺)建立。化学镀铜用于制作种子层，激光直接成像(LDI)用于打开光刻胶，PCB(印刷电路板)镀铜用于制作rdl的导体接线。可靠性评估，如热循环测试也被执行。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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