2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第5页

Software-based Pauli tracking in fault-tolerant quantum circuits 容错量子电路中基于软件的泡利跟踪

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.137

A. Paler, S. Devitt, K. Nemoto, I. Polian

引用次数: 19

Modeling steep slope devices: From circuits to architectures 陡坡设备建模:从电路到架构

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.149

Karthik Swaminathan, M. Kim, Nandhini Chandramoorthy, B. Sedighi, Robert Perricone, J. Sampson, N. Vijaykrishnan

{"title":"Modeling steep slope devices: From circuits to architectures","authors":"Karthik Swaminathan, M. Kim, Nandhini Chandramoorthy, B. Sedighi, Robert Perricone, J. Sampson, N. Vijaykrishnan","doi":"10.7873/DATE.2014.149","DOIUrl":"https://doi.org/10.7873/DATE.2014.149","url":null,"abstract":"Steep Slope devices, with Heterojunction Tunnel FETs (TFETs) in particular, have been proposed as a viable solution to overcome the subthreshold slope limitation in existing CMOS technology and achieve ultra-low voltage operation with acceptable performance. However, state-of-the-art FinFET technologies continue to demonstrate superior performance than steep slope devices in application domains demanding peak single threaded performance. In this context, we examine different computing paradigms where TFET technologies can be used, not just as a `drop in' replacement, but as an additional parameter to augment the architectural design space. This greatly widens the scope of optimizations for performance and power. We investigate the tradeoffs between device and architectures in general purpose processors when performance, power and temperature are individually constrained. We also synthesize examples of domain-specific accelerators used in computer vision using in-house TFET standard cell libraries to demonstrate the energy benefits of designing TFET-based accelerators. We demonstrate that synthesizing these accelerators using TFETs reduces energy by over 6X in comparison to an equivalent iso-voltage CMOS-based design and by over 30% in comparison to an iso-performance CMOS design.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"24 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72660567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Co-optimization of memory BIST grouping, test scheduling, and logic placement 内存BIST分组、测试调度和逻辑布局的协同优化

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.209

A. Kahng, Ilgweon Kang

{"title":"Co-optimization of memory BIST grouping, test scheduling, and logic placement","authors":"A. Kahng, Ilgweon Kang","doi":"10.7873/DATE.2014.209","DOIUrl":"https://doi.org/10.7873/DATE.2014.209","url":null,"abstract":"Built-in self-test (BIST) is a well-known design technique in which part of a circuit is used to test the circuit itself. BIST plays an important role for embedded memories, which do not have pins or pads exposed toward the periphery of the chip for testing with automatic test equipment. With the rapidly increasing number of embedded memories in modern SOCs (up to hundreds of memories in each hard macro of the SOC), product designers incur substantial costs of test time (subject to possible power constraints) and BIST logic physical resources (area, routing, power). However, only limited previous work addresses the physical design optimization of BIST logic; notably, Chien et al. [7] optimize BIST design with respect to test time, routing length, and area. In our work, we propose a new three-step heuristic approach to minimize test time as well as test physical layout resources, subject to given upper bounds on power consumption. A key contribution is an integer linear programming ILP framework that determines optimal test time for a given cluster of memories using either one or two BIST controllers, subject to test power limits and with full comprehension of available serialization and parallelization. Our heuristic approach integrates (i) generation of a hypergraph over the memories, with test time-aware weighting of hyperedges, along with top-down, FM-style min-cut partitioning; (ii) solution of an ILP that comprehends parallel and serial testing to optimize test scheduling per BIST controller; and (iii) placement of BIST logic to minimize routing and buffering costs. When evaluated on hard macros from a recent industrial 28nm networking SOC, our heuristic solutions reduce test time estimates by up to 11.57% with strictly fewer BIST controllers per hard macro, compared to the industrial solutions.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"11 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74148028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Hardware/software approach for code synchronization in low-power multi-core sensor nodes 低功耗多核传感器节点代码同步的硬件/软件方法

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.181

R. Braojos, A. Dogan, I. Beretta, G. Ansaloni, David Atienza Alonso

{"title":"Hardware/software approach for code synchronization in low-power multi-core sensor nodes","authors":"R. Braojos, A. Dogan, I. Beretta, G. Ansaloni, David Atienza Alonso","doi":"10.7873/DATE.2014.181","DOIUrl":"https://doi.org/10.7873/DATE.2014.181","url":null,"abstract":"Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabilities. On the other hand, long-term signal processing in WBSNs must be provided within their highly constrained energy budget. In this context, parallel processing effectively increases the power efficiency of WBSNs, but only if the execution can be properly synchronized among computing elements. To address this challenge, in this work we propose a hardware/software approach to synchronize the execution of bio-signal processing applications in multi-core WBSNs. This new approach requires little hardware resources and very few adaptations in the source code. Moreover, it provides the necessary flexibility to execute applications with an arbitrarily large degree of complexity and parallelism, enabling considerable reductions in power consumption for all multi-core WBSN execution conditions. Experimental results show that a multi-core WBSN architecture using the illustrated approach can obtain energy savings of up to 40%, with respect to an equivalent single-core architecture, when performing advanced bio-signal analysis.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"49 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84799724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Coverage evaluation of post-silicon validation tests with virtual prototypes 使用虚拟原型对后硅验证测试进行覆盖率评估

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.331

Kai Cong, Li Lei, Zhenkun Yang, Fei Xie

{"title":"Coverage evaluation of post-silicon validation tests with virtual prototypes","authors":"Kai Cong, Li Lei, Zhenkun Yang, Fei Xie","doi":"10.7873/DATE.2014.331","DOIUrl":"https://doi.org/10.7873/DATE.2014.331","url":null,"abstract":"High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81887018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A Linux-governor based Dynamic Reliability Manager for android mobile devices 基于linux调控器的android移动设备动态可靠性管理器

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.117

Pietro Mercati, Andrea Bartolini, Francesco Paterna, T. Simunic, L. Benini

引用次数: 34

Minimally buffered single-cycle deflection router 最小缓冲单周期偏转路由器

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.323

Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, M. Mutyam

引用次数: 17

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints 具有制造约束的可重构单电子晶体管阵列的面积最小化合成

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.1145/2906360

Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang

引用次数: 12

Connecting different worlds — Technology abstraction for reliability-aware design and Test 连接不同的世界——可靠性感知设计和测试的技术抽象

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.265

Ulf Schlichtmann, V. Kleeberger, J. Abraham, A. Evans, C. Gimmler-Dumont, M. Glaß, A. Herkersdorf, S. Nassif, N. Wehn

引用次数: 7

Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction 联合虚拟探针:联合探索多个测试项目的空间模式，用于高效硅表征和测试预测

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.240

Shuang-Wang Zhang, Fan Lin, Chun-Kai Hsu, K. Cheng, Hong Wang

{"title":"Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction","authors":"Shuang-Wang Zhang, Fan Lin, Chun-Kai Hsu, K. Cheng, Hong Wang","doi":"10.7873/DATE.2014.240","DOIUrl":"https://doi.org/10.7873/DATE.2014.240","url":null,"abstract":"Virtual Probe (VP), proposed for characterization of spatial variations and for test time reduction, can effectively reconstruct the spatial pattern of a test item for an entire wafer using measurement values from only a small fraction of dies on the wafer. However, VP calculates the spatial signature of each test item separately, one item at a time, resulting in very long runtime for complex chips which often require hundreds, or even thousands, of test items in production. In this paper, we propose a new method, named Joint Virtual Probe (JVP), which can jointly derive spatial patterns of multiple test items. By simultaneously handling a large group of test items, JVP significantly reduces the overall runtime. And the prediction accuracy can also be improved because of JVP's implicit use of inter-test-item correlations in predicting spatial patterns. The experimental results on two industrial products, with 277 and 985 parametric test items in the production test programs respectively, demonstrate that, JVP achieves an average speedup of ~ 170X and ~ 50X over VP in the pre-test analysis and the test application phases respectively, as well as a slightly higher prediction accuracy than VP.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"59 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80458282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14