2014 20th International Conference on Ion Implantation Technology (IIT)最新文献_第9页

Sputtering and chemical modification of solid surfaces using oxygen ion beams 用氧离子束溅射和固体表面的化学修饰

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6939980

G. Takaoka, H. Ryuto, M. Takeuchi, Ryou Tsujinaka

引用次数: 0

Simulation of 3D FinFET doping profiles introduced by ion implantation and the impact on device performance 离子注入引入的三维FinFET掺杂谱模拟及其对器件性能的影响

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940008

Liping Wang, A. Brown, B. Cheng, A. Asenov

引用次数: 0

Millisecond annealing for advanced device fabrications 用于先进器件制造的毫秒退火

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940020

Y. Wang, Shaoyin Chen, Xiaoru Wang, M. Shen

引用次数: 1

New Trench gate LDMOS for low power applications 新沟槽栅极LDMOS低功耗应用

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940006

Dawei Xu, Xinhong Cheng, Zhong Jian, Linyan Shen, C. Xia, D. Cao, Li Zheng, Yu Yuehui

引用次数: 0

Thermal processing for continued scaling of semiconductor devices 半导体器件持续缩放的热处理

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6939954

S. Sharma, W. Aderhold, K. Raman Sharma, A. Mayur

引用次数: 3

Silicon defects characterization for low temperature ion implantation and spike anneal processes 低温离子注入和尖峰退火过程中硅缺陷的表征

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940014

G. Margutti, Diego Martirani Paolillo, Marco De Biase, L. Latessa, M. Barozzi, E. Demenev, L. Rubin, C. Spaggiari

{"title":"Silicon defects characterization for low temperature ion implantation and spike anneal processes","authors":"G. Margutti, Diego Martirani Paolillo, Marco De Biase, L. Latessa, M. Barozzi, E. Demenev, L. Rubin, C. Spaggiari","doi":"10.1109/IIT.2014.6940014","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940014","url":null,"abstract":"In the last years a lot of effort has been directed in order to reduce ion implantation damage, which can be detrimental for silicon device performances. Implantation's dose rate and temperature were found to be two important factors to modulate residual damage left in silicon after anneal. In this work high dose rate, low temperature, high dose arsenic and boron implantations are compared to the corresponding low dose rate, room temperature processes in terms of silicon lattice defectiveness and dopant distribution, before and after anneal is performed. The considered implant processes are the one typically used to form a source/drain region in a CMOS process flow in the submicron technology node. A spike anneal process was applied to activate the dopant. Low temperature, high dose rate implantations have found to be effective in reducing silicon extended defects with a negligible effect on the profile of the activated dopant. Experimental set up, results and possible explanation will be reported and discussed in the paper.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"85 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73555470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Study of AsH3 Plasma Immersion Ion Implantation using PULSION® 使用pulusl®进行AsH3等离子体浸没离子注入的研究

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6939963

J. Duchaine, F. Torregrosa, Y. Spiegel, G. Borvon, S. Qin, Y. Hu, A. Mcteer

{"title":"Study of AsH3 Plasma Immersion Ion Implantation using PULSION®","authors":"J. Duchaine, F. Torregrosa, Y. Spiegel, G. Borvon, S. Qin, Y. Hu, A. Mcteer","doi":"10.1109/IIT.2014.6939963","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939963","url":null,"abstract":"Plasma immersion ion implantation (PIII) technology is known as an alternative to overcome the limitations of conventional beam line ion implantation for shallow, high dose and 3D doping on advanced memory and logic devices. This technique also shows a better CoO as the result of higher productivity, smaller footprint and lower operating costs. Implementation in production for P-type doping and development of N-type applications address issues from the challenges linked to the use of hydrides, especially in the case of AsH3 and PH3. Problems of excessive deposition lead to difficult process integration and possible safety issues such as wafer out-gassing. [1]. Higher priced gases coupled with higher gas consumption compared to beam line are often mentioned as limitations. In this paper we present a full characterization (done at Micron and at IBS) of AsH3 plasma implantation using PULSION® (PIII tool produced by IBS). Due to its unique remote source design, PULSION® allows a wider process window using lower gas flows [2]. These design advantages minimize the before mentioned drawbacks allowing easier process integration [3]. AES (Auger Electron Spectroscopy), ARXPS (Angle Resolution X-ray Photoelectron Spectroscopy), TOF-SIMS & D-SIMS (Secondary Ion Mass Spectrometry), and TEM (Transmission Electron Microscopy) analysis are used to study deposition, doping profiles, and amorphization as a function of acceleration voltage and dose. The effect of dose on sheet resistance after Spike anneal is discussed, as well as the effect of possible hydrogen dilution. Out-gassing measurements are also presented.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76001395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Thermal cycle annealing and its application to arsenic-ion implanted HgCdTe 热循环退火及其在砷离子注入HgCdTe中的应用

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940053

S. Simingalam, P. Wijewarnasuriya, M. V. Rao

{"title":"Thermal cycle annealing and its application to arsenic-ion implanted HgCdTe","authors":"S. Simingalam, P. Wijewarnasuriya, M. V. Rao","doi":"10.1109/IIT.2014.6940053","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940053","url":null,"abstract":"Arsenic ion-implantation is a standard device processing step to create selective area p+-HgCdTe (MCT) regions in planar devices. One of the issues associated with the ion-implantation process is the significant structural damage to the MCT epilayer. These structural defects limit the performance of diodes via significant tunneling reverse-bias dark currents. After ion-implantation, a high temperature annealing step is required to activate the implant (arsenic) by moving it into the tellurium sublattice and also to heal the lattice damage caused by the implantation process. In this study, we have used thermal cycle annealing (TCA) to decrease ion implantation damage. In TCA, we rapidly heat and cool an MCT sample, which provides an additional degree of freedom that is not obtainable with conventional annealing. We have successfully performed TCA for dislocation defect reduction in in-situ indium-doped MCT with limited inter-diffusion between the absorber layer and cadmium rich cap layer. We also investigated the application of TCA to arsenic ion-implanted MCT. Defects were studied using scanning electron microscopy (SEM) after subjecting the samples to Benson etching to decorate the defects. Mercury-deficient and tellurium-saturated overpressure anneals were performed in an attempt to increase mercury vacancy concentrations and, thereby, increase dislocation climb. Such anneals significantly increased the etch pit density (EPD) in both ion-implanted and un-implanted MCT. By cycle annealing, we have also shown EPD reduction in arsenic ion-implanted, long bar shaped MCT mesas formed on CdTe/Si substrates.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89378761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Ion beams, thermal processes and lithographic challenges 离子束，热加工和光刻的挑战

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6939966

H. Levinson, T. Brunner

{"title":"Ion beams, thermal processes and lithographic challenges","authors":"H. Levinson, T. Brunner","doi":"10.1109/IIT.2014.6939966","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939966","url":null,"abstract":"Among the challenges with which lithographers are currently grappling, the issues of line-edge roughness (LER) and non-linear overlay errors intersect the concerns of ion implantation and thermal process engineers. LER, and the associated metric for contact holes, local critical dimension uniformity (LCDU), must be small to meet the requirements of advanced nodes. Photon shot-noise-induced LER and LCDU diminution, which can benefit from high resist exposure doses, must be balanced with exposure tool throughput requirements for meeting cost targets for Moore's Law. Because very small improvements in LER and LCDU can require substantial increases in resist exposure doses, post-lithographic techniques for reducing LER and LCDU can have sizable salutary impact on overall wafer costs. The impact of LER on circuit performance depends on the spatial frequencies comprising the LER, and the criticality of particular ranges of spatial frequencies may shift as a consequence of transitions to new types of devices. LER can be reduced post-lithographically by using charged particle beams. Non-linear wafer distortions, which can result from thermal processes and the etching of high-stress films, are problematic for overlay control. Correction of non-linear overlay errors requires the use of a large number of alignment sites and overlay measurements, again resulting in a trade-off between process control and wafer cost. The impact of these distortions on overlay can be predicted quantitatively by measurements of out-of-plane wafer warp. Such measurements can be used to develop processes with intrinsically low distortion and for maintaining process control in manufacturing.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"40 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77689770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of charge build-up in NO nitrided gate oxide on 4H-SiC during Fowler-Nordheim injection and fabrication of 4H-SiC Lateral Double-Implanted MOSFETs Fowler-Nordheim注入过程中4H-SiC上NO氮化栅氧化物电荷积累的研究及4H-SiC横向双植入mosfet的制备

2014 20th International Conference on Ion Implantation Technology (IIT) Pub Date : 2014-10-30 DOI: 10.1109/IIT.2014.6940051

J. Moon, W. Bahng, I. Kang, Sang Cheol Kim, N. Kim

引用次数: 0