{"title":"PC-based human face recognition system","authors":"R. Y. Wong, James Calia","doi":"10.1109/MWSCAS.1991.252031","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252031","url":null,"abstract":"Measurements from features of a human such as eyes, nose, mouth, and face profile are used for face recognition. Images of human faces, each 256*200 in size with 64 shades of gray, are stored in a gray-level referenced file. Face matchings were performed in two stages. In the first stage, image processing techniques were used to extract six features from each of the gray-level images. Each face is represented by a vector of six dimensions and is stored in the six-feature referenced file along with the gray-level images. The same features from an unlabeled face were then extracted and a search was performed to locate the most likely candidates in the six-feature file. Computations were greatly simplified since matching was based on six numbers and many of the unlikely candidates were eliminated at this stage. The second stage involved the matching of all facial features of the unlabeled face to those of the most likely candidates in the gray-level file. Time required to match a face was greatly reduced since comparison of all facial features was done on relatively fewer most likely candidates. Experimental results indicated that with a small referenced file of ten persons the system was able to correctly classify unlabeled faces 80% of the time. Currently a computing time of 15 minutes is needed for each classification.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"641-644 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87691820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the stability of adaptive controllers for robotic manipulators","authors":"G. M. Nicoletti","doi":"10.1109/MWSCAS.1991.251979","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.251979","url":null,"abstract":"The design of an adaptive force and position control system with adjustable gains for robotic manipulators is presented. The design is based on a hybrid feedforward-feedback architecture. The force control module is developed in a feedforward loop and is governed by a control law which includes time-dependent proportional, integral and derivative gains. The position control module is developed in a feedback loop and is governed by a linear adaptive control law which include position, velocity, and acceleration gains. The control gains are continually adapted according to well-defined adaptation schemes formulated to minimize force and position error signals, respectively. Stability considerations in the sense of Lyapunov are formulated, and an outline of a proposed simulation scheme is presented.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"950-953 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88439844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A SPICE macromodel for an adjustable positive voltage regulator","authors":"G.M. Wierzba, K. Noren","doi":"10.1109/MWSCAS.1991.252088","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252088","url":null,"abstract":"A macromodel has been developed for the LM117 adjustable positive voltage regulator. This model predicts AC, DC, transient, and power-up responses. Design formulas for finding the component values of the macromodel which are based on pin measurements are presented. The methodology of development is presented along with experimental and simulated results.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"610-614 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72851850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testable CMOS design for robust and logical testability of stuck-open/stuck-on faults","authors":"J.-M. Lee, S.-M. Kang","doi":"10.1109/MWSCAS.1991.252035","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252035","url":null,"abstract":"A novel robust testable CMOS design technique is proposed to detect all stuck-open and stuck-on faults by single test patterns for the logic circuit and two pattern sequences for the circuit added for testability. The proposed technique adds one transistor per gate for stuck-open fault testing and two transistors for stuck-on faults per gate or multi-level circuit. Thus, for multilevel circuits consisting of N gates, only N+2 additional transistors are required. The extra transistors for stuck-open faults are also capable of monitoring the output signals of gates, by which the observability of the circuit can be enhanced. The proposed technique uses single test patterns for the logic circuit, and hence the overall testing procedure and cost are significantly reduced.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"203 1-2","pages":"623-628 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91489030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A neural network to approximate nonlinear functions","authors":"A. Bernardini, S. de Fina","doi":"10.1109/MWSCAS.1991.252103","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252103","url":null,"abstract":"A neural network approach to the problem of approximating any nonlinear continuous function is provided. The results obtained are related to the single-variable case, but the main conclusions can be generalized for the multidimensional case. The net is a modified perceptron with one hidden layer of sigmoidal units and two intermediate output linear units that are linearly combined to provide the final mapping. In particular, the problem concerning the starting weight configuration and the conditions that guarantee the correct learning with a random setting is analyzed. Other neural computations providing similar solutions to the approximation problem suffer from convergence to a local minimum if the starting network configuration is arbitrarily chosen, thus requiring a previous computation of the interpolating parameters that provides a weights setting quite close to the global optimum. In the present approach, one of the intermediate outputs is somewhat related to the curve derivative so that the overall net behavior can be viewed as a curve derivative integrator in which the second output is related to the constant term to be added to the undefined integral calculation. Simulation results, obtained after randomly setting the starting weight configuration, show excellent performance for all the trained functions.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"545-548 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82121401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inexpensive shareware programs useful in EE coursework","authors":"R. Stuffle, L. Stuffle","doi":"10.1109/MWSCAS.1991.252143","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252143","url":null,"abstract":"The authors present the results of a continuing survey of public-domain and shareware programs useful in electrical engineering (EE) education. Brief descriptions of those they feel are simultaneously sufficient for classwork applications and reasonable in cost are presented. Attention is given to software for graphing/plotting, word processing, graphics/schematic drawing, simulation, and miscellaneous special applications.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"130-133 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85935375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Direct variational solutions for linear dissipative oscillator using Lagrangian with reverse time scales","authors":"V. M. Fatic","doi":"10.1109/MWSCAS.1991.252041","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252041","url":null,"abstract":"A new Lagrangian with reverse time scales is used for direct variational approximation of the solution of a linear dissipative oscillator. Very accurate global approximations are obtained by polynomial test functions of low order. The main goal of the present work is to verify a novel method for variational formulation of dissipative systems. It is. concluded that the new Lagrangian is not only correct, but is also a reliable tool for direct variational solutions of both boundary-value and initial-value problems.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"157 1","pages":"295-298 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85339444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Split-capacitive load variable taper buffer design","authors":"S. Vemuru, E. Smith","doi":"10.1109/MWSCAS.1991.251988","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.251988","url":null,"abstract":"A split-capacitive load variable taper model for buffer design is proposed. For similar propagation delays, the proposed model results in buffer designs that take significantly less silicon area and less power dissipation compared to conventional FT (fixed taper) design. For lower capacitive loads, the FT designs are still better. Area, propagation delay, and power dissipation comparisons are made between the proposed and conventional designs using SPICE simulations.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"815-818 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84114552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of switched capacitor filter using bilinear transformation","authors":"S. Hirano, E. Hayahara","doi":"10.1109/MWSCAS.1991.252097","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252097","url":null,"abstract":"The authors describe a design approach of the SCF (switched capacitor filter) simulating the doubly resistively terminated LC filter which is based on the concept of the bilinear transformation. The design approach is experimentally confirmed by the measurement of a test circuit with discrete elements. The features of this design approach are as follows: the SCF structure is the same as that based on the LDI transformation, the SCF structure requires no sample and hold circuits at the front and back, and the aperture effect is approximately compensated. Consequently, the total circuit that includes the SCF, the prefilter, and the postfilter can become simple and small. This design approach is effective in the case of using the SCF with the prefilter and the postfilter on the same IC chip.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"572-575 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90998223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Systolic architectures for parallel Fourier transform","authors":"T. Baradaran-Seyed, L. G. Johnson, B. Karimi","doi":"10.1109/MWSCAS.1991.252044","DOIUrl":"https://doi.org/10.1109/MWSCAS.1991.252044","url":null,"abstract":"Novel systolic architectures are proposed for the computation of the Fourier transform based on the generation of the coefficients of the transform during the computation. These architectures require fewer input/output pins on the chip. The novel architectures are also extremely modular and cascadable, and thus are amenable to efficient VLSI implementation. The VLSI complexity of the architectures is compared with that of existing parallel architectures.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"48 1","pages":"283-286 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91199029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}