Split-capacitive load variable taper buffer design

Abstract

A split-capacitive load variable taper model for buffer design is proposed. For similar propagation delays, the proposed model results in buffer designs that take significantly less silicon area and less power dissipation compared to conventional FT (fixed taper) design. For lower capacitive loads, the FT designs are still better. Area, propagation delay, and power dissipation comparisons are made between the proposed and conventional designs using SPICE simulations.<>