1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)最新文献_第6页

A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning 时间复用FPGA分区中调度压缩的图论优化算法

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810683

Huiqun Liu, D. F. Wong

引用次数: 12

Memory bank customization and assignment in behavioral synthesis 行为合成中的记忆库定制与分配

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810697

P. Panda

{"title":"Memory bank customization and assignment in behavioral synthesis","authors":"P. Panda","doi":"10.1109/ICCAD.1999.810697","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810697","url":null,"abstract":"With increasing design complexity and chip area, on-chip memory has become an important component whose integration needs to be addressed during system design. Modern embedded DRAM technology allows for large amounts of on-chip memory space. However, in order to utilize the available memory intelligently, the memory has to be appropriately customized for the specific application. We address the topic of incorporating the application-specific customization of memory bank configuration into behavioral synthesis. The strategy involves a partitioning of behavioral arrays into memory banks based on a cost function that estimates the performance implications. For a given candidate partition, we present a heuristic for determining the access sequence that minimizes page misses in a bank while respecting data dependences. The output of the exploration is a graph displaying the variation of delay and memory area with the bank configuration. Our experiments on several memory-intensive examples confirm that the exploration results can provide critical feedback to the designer about the optimal memory configuration for a given application.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84880679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Factoring logic functions using graph partitioning 使用图划分分解逻辑函数

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810648

M. Golumbic, A. Mintz

引用次数: 23

Practical considerations for passive reduction of RLC circuits 无源减小RLC电路的实际考虑

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810652

Altan Odabasioglu, M. Çelik, L. Pileggi

引用次数: 54

Fault modeling and simulation for crosstalk in system-on-chip interconnects 片上系统互连串扰的故障建模与仿真

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810665

M. Cuviello, S. Dey, Xiaoliang Bai, Yi Zhao

{"title":"Fault modeling and simulation for crosstalk in system-on-chip interconnects","authors":"M. Cuviello, S. Dey, Xiaoliang Bai, Yi Zhao","doi":"10.1109/ICCAD.1999.810665","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810665","url":null,"abstract":"System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78926682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 244

Integrated floorplanning and interconnect planning 综合平面规划和互联规划

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1007/978-1-4757-3415-7_1

Hung-Ming Chen, H. Zhou, Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, N. Sherwani

引用次数: 77

AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths AKORD:用于数字数据路径的晶体管级和混合晶体管/栅极级放置工具

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810628

T. Serdar, C. Sechen

引用次数: 15

New methods for speeding up computation of Newton updates in harmonic balance 加快谐波平衡牛顿更新计算的新方法

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810622

M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov

引用次数: 4

Timing-driven partitioning for two-phase domino and mixed static/domino implementations 用于两阶段domino和混合静态/domino实现的定时驱动分区

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810631

Min Zhao, S. Sapatnekar

引用次数: 4

What is the cost of delay insensitivity? 延迟不敏感的代价是什么?

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810668

H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev

引用次数: 21