1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)最新文献_第10页

An implicit connection graph maze routing algorithm for ECO routing 一种用于ECO路由的隐式连接图迷宫路由算法

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810642

J. Cong, Jie Fang, Kei-Yong Khoo

引用次数: 60

Performance optimization under rise and fall parameters 升降参数下的性能优化

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810646

R. Murgai

{"title":"Performance optimization under rise and fall parameters","authors":"R. Murgai","doi":"10.1109/ICCAD.1999.810646","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810646","url":null,"abstract":"Typically, cell parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. The performance optimization algorithms, however, assume a single value for each parameter. No work has been done to study the impact of separate rise and fall values on the complexity of optimization. We take the first step towards understanding this impact. We pick two problems that have polynomial-time complexities if a single value for each cell parameter is assumed. The first problem is that of buffer insertion on a fixed topology net to maximize the required time at the source of the net. The second is the gate resizing problem (and the more general technology mapping problem) for minimizing the circuit delay under the simplest, load-independent delay model. We show that under separate rise and fall parameters, both these problems become NP-complete. To the best of our knowledge, this is the first such result showing the effect of rise and fall parameters on the complexity of performance optimization problems. We then address the important question of devising a good practical algorithm for local fanout optimization.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87651654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Synthesis for multiple input wires replacement of a gate for wiring consideration 合成多输入导线替换一个栅极布线考虑

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810633

Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu

引用次数: 6

Improving coverage analysis and test generation for large designs 改进大型设计的覆盖率分析和测试生成

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810714

J. P. Bergmann, M. Horowitz

{"title":"Improving coverage analysis and test generation for large designs","authors":"J. P. Bergmann, M. Horowitz","doi":"10.1109/ICCAD.1999.810714","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810714","url":null,"abstract":"State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing the state and edge coverage provided by tests with that which is possible in the design's state graph, the designer can estimate how well tested the design is and identify areas that need better testing. Unfortunately, for many interesting designs, the full state graph may be too large to fully explore, or if it is explorable, the resulting coverage may be so low as to provide limited feedback. Several techniques have been proposed that identify and work with an interesting subset of the design's state machines, but they still require computing the full state graph before projecting it. In this paper we discuss projection directed state exploration, in which a projection from the full graph is found while exploring only the relevant portion of the full graph. Even with this limited exploration, BDD size blowup is still a problem. To deal with this, we have also developed several interactive tools that provide feedback to the designer, and allow them to add hints to help with the exploration.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79335746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

TICER: Realizable reduction of extracted RC circuits 可实现的减少提取RC电路

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810649

B. Sheehan

引用次数: 100

Optimum loading dispersion for high-speed tree-type decision circuitry 高速树形决策电路的最佳负载色散

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810705

J. H. Jiang, I. Jiang

{"title":"Optimum loading dispersion for high-speed tree-type decision circuitry","authors":"J. H. Jiang, I. Jiang","doi":"10.1109/ICCAD.1999.810705","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810705","url":null,"abstract":"With increasing density and capacity due to technology scaling, augmenting data (especially in semiconductor memories) burden selection circuitry with exponentially growing capacitive loads. This tendency violates stringent timing requirements. This work ameliorates the situation for k-stage tree-type decision circuitry. We show that for a k-stage binary decision tree, there always exists an optimum solution such that, after the select-signal arrangement, the worst case loading among select signals equals a lower bound. Our proposed procedure not only provides an optimum solution but also minimizes the loading variance. The worst case loading can be reduced up to nearly k/2 times, thus speeding up and saving power up to W2 times or so for the select signal with the heaviest loading. In contrast, excluding one unit-loading select signal, the empirical variance of the remaining (k-1) signals is always less than 1 instead of diverging. Hence, our approach, for timing-driven layout synthesis, is competent to design high-performance tree-type decision circuitry with more accurate timing and power prediction. In addition, by the presented approach, we can have the alternative of optimizing either for k-stage or for (k-1)-stage, meanwhile possibly minimizing the other. Our algorithm, also, can easily be extended for a general k-stage decision tree with r descendants per node, not restricted to a binary tree; the resultant worst case loading could be quite close to the lower bound and reduced up to nearly k(r-1)/r times.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82811312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Concurrent logic restructuring and placement for timing closure 并发逻辑重构和定时闭包的放置

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810615

J. Lou, Wei Chen, Massoud Pedram

引用次数: 28

Test scheduling for core-based systems 基于核心的系统的测试调度

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810681

K. Chakrabarty

引用次数: 59

Efficient diagnosis of path delay faults in digital logic circuits 数字逻辑电路中路径延迟故障的有效诊断

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810696

P. Pant, A. Chatterjee

引用次数: 12

Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization 基于无前瞻自适应乐观保守同步的VLSI系统分布式仿真

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) Pub Date : 1999-11-07 DOI: 10.1109/ICCAD.1999.810701

D. Lungeanu, C. Shi

{"title":"Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization","authors":"D. Lungeanu, C. Shi","doi":"10.1109/ICCAD.1999.810701","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810701","url":null,"abstract":"The paper presents a novel protocol for parallel and distributed simulation of VLSI systems. It is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. Second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. All these features make it very convenient and practical, extending the class of applications to at least all VHDL circuits, including delta cycle. The proposed protocol has been implemented and used for VHDL simulation. Experimental results on several large VHDL circuits (between 1411 and 14704 processes) have shown promising linear speedups. We also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. This protocol may have a strong impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86063446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14