Efficient diagnosis of path delay faults in digital logic circuits

Abstract

A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.