2007 IEEE International Test Conference最新文献_第9页

SPARTAN: a spectral and information theoretic approach to partial-scan 部分扫描的光谱和信息论方法

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437620

Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal

{"title":"SPARTAN: a spectral and information theoretic approach to partial-scan","authors":"Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal","doi":"10.1109/TEST.2007.4437620","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437620","url":null,"abstract":"We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of maximum entropy), which improves testability. We propose using partial-scan for testing, to maximize fault coverage (FC), reduce test volume (TV), reduce test application time (TAT), and reduce test power (TP) but we allow for full-scan during silicon debug. Full-scan is commonly used for testing, to reduce sequential automatic test-pattern generation (ATPG) to the complexity of combinational ATPG, but comes with serious TV, TAT, and TP overheads. Partial-scan significantly reduces circuit delay, when compared to full-scan, because critical flip-flops in the circuit data path do not have the extra hardware for full-scan, and therefore are roughly 5% faster, and use 10% less area. This is particularly critical for microprocessors. The HITEC ATPG program generated results for this new partial-scan algorithm.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75103860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Protocol requirements in an SJTAG/IJTAG environment SJTAG/IJTAG环境中的协议需求

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437658

G. Carlsson, J. Holmqvist, E. Larsson

引用次数: 5

How to ensure zero defects from the beginning with semiconductor test methods 如何用半导体测试方法从一开始就保证零缺陷

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437697

Bernd Gessner

引用次数: 3

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation 自动处理可编程的产品时钟生成(OPCG)电路，用于延迟测试矢量生成

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437610

A. Uzzaman, Bibo Li, T. Snethen, B. Keller, Gary Grise

引用次数: 4

Principles and results of some test cost reduction methods for ASICs 一些降低asic测试成本的方法的原理和结果

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437702

P. Maxwell

引用次数: 4

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test PMScan:一种电源管理扫描，在扫描测试期间同时降低动态和泄漏功率

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437598

V. Devanathan, C. Ravikumar, R. Mehrotra, V. Kamakoti

引用次数: 26

A low cost test data compression technique for high n-detection fault coverage 针对高n检测故障覆盖率的低成本测试数据压缩技术

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437612

Seongmoon Wang, Zhanglei Wang, Wenlong Wei, S. Chakradhar

引用次数: 2

Power-aware test: Challenges and solutions 功耗感知测试:挑战和解决方案

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437660

S. Ravi

引用次数: 107

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs 用于检测soc核心-外部互连信号完整性故障的测试封装器设计

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437572

Q. Xu, Yubin Zhang, K. Chakrabarty

{"title":"Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs","authors":"Q. Xu, Yubin Zhang, K. Chakrabarty","doi":"10.1109/TEST.2007.4437572","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437572","url":null,"abstract":"As feature sizes continue to shrink for newer process technologies, signal integrity (SI) is emerging as a major concern for core-based system-on-a-chip (SoC) integrated circuits. To effectively test SI faults on core-external interconnects, core test wrappers need to be able to generate appropriate transitions at a wrapper output cell (WOC) on the driving side and detect the signal integrity loss at a wrapper input cell on the receiving side. In current wrapper designs, the WOCs for a victim interconnect and its aggressors make transitions at the same time with a common test clock signal in test mode, which is different from the functional mode. This is not adequate for SI test because the time elapsed between the transition of the victim and the transitions of its aggressors significantly affects the behavior of Si-related errors. To address this problem, we propose new IEEE Std. 1500-compliant wrapper designs that are able to apply SI test at functional mode or make transitions with various pre-defined skews between a victim line and its aggressors. We also introduce a novel overshoot detector inside the proposed wrapper. Experimental results show that the proposed wrapper designs are more effective for detecting Si-related errors when compared to existing techniques, with a moderate amount ofDFT overhead.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87480284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Interconnect open defect diagnosis with minimal physical information 互连开放缺陷诊断与最小的物理信息

2007 IEEE International Test Conference Pub Date : 2007-10-01 DOI: 10.1109/TEST.2007.4437580

Chen Liu, Wei Zou, S. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang

{"title":"Interconnect open defect diagnosis with minimal physical information","authors":"Chen Liu, Wei Zou, S. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang","doi":"10.1109/TEST.2007.4437580","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437580","url":null,"abstract":"We consider the problem of determining the location of open defects in interconnects of deep submicron (DSM) designs. The target defect sites for this work are the vias in interconnects which are known to be defect prone. It is known that in DSM designs below 90 nm technology the circuit parameters may vary widely from nominal or design values and process variations make them less predictable. Thus it becomes necessary to develop methods for locating defect sites without accurate knowledge of circuit parameters. Logic diagnosis which is based on gate level net lists is one such method but the resolution of defect sites obtained by logic diagnosis is considered to be unacceptably low for locating open vias. We investigate a procedure that uses minimal information beyond the net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82620990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19