Principles and results of some test cost reduction methods for ASICs

Abstract

This paper describes several different approaches to obtain test cost reduction, with emphasis on experimental results obtained for a class of ASICs, although the techniques are general. A review is given of some architectural approaches before giving details of techniques which address reduction in test time. The importance of the gathering and analysis of production data is highlighted with a view to better balance wafer and package tests, eliminate ineffective tests, truncate existing tests and carefully examine at which voltage a test should be run. Stress testing is also discussed with the goal of optimizing tests which are run before and after stress.