2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers最新文献_第7页

A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of −193.5dBc/Hz 一种10mW 37.8GHz电流再分配BiCMOS压控振荡器，平均fof为−193.5dBc/Hz

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487677

Qiyang Wu, T. Quach, A. Mattamana, S. Elabd, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil

{"title":"A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of −193.5dBc/Hz","authors":"Qiyang Wu, T. Quach, A. Mattamana, S. Elabd, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil","doi":"10.1109/ISSCC.2013.6487677","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487677","url":null,"abstract":"The continued scaling of digital CMOS technology has enabled mm-Wave VCOs with record figures of merit [1-5]. This is mainly driven by the increase in cutoff frequency and decrease in power consumption brought by lower supply voltages. However, at mm-Wave, challenges such as low Q-factor of the tuning varactors and switched capacitors result in a sharp degradation in the resonator Q. For an NMOS LC-VCO (Fig. 8.8.1), a large bias current and high transconductance (gm) are needed to maintain a given oscillation amplitude and to satisfy the startup condition. Since gm has a weak dependency on current in strong inversion, it can primarily be increased by enlarging the device width, W1, as illustrated in Fig. 8.8.2. Further degradation in the device gm is experienced when the VCO operates near the transistor cutoff frequency, necessitating an even larger W1 (Fig. 8.8.2). This results in a large fixed capacitance Cfix1 and hence a limited VCO tuning range (TR) [1,2]. It can also be shown that for the same bias current (i.e. output swing), increasing W1 comes at the expense of large thermal (1/f2) noise. This can be illustrated by examining the excess noise factor F, defined as the ratio between the transistors' switching noise and the tank resistor noise [6]. As depicted in Fig. 8.8.2, an extra 5dB of 1/f2 noise is added to the VCO output when the transistor W1 is increased from 20μm to 60μm, which is required to meet a 2× startup margin. Moreover, increasing W1 leads to a higher contribution of 1/f3 noise from up-converted 1/f noise [7].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"8 1","pages":"150-151"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87498521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor 1/4英寸800万像素背照堆叠CMOS图像传感器

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487825

S. Sukegawa, T. Umebayashi, T. Nakajima, Hiroshi Kawanobe, K. Koseki, I. Hirota, T. Haruta, Masanori Kasai, Koji Fukumoto, T. Wakano, Keishi Inoue, Hiroshi Takahashi, T. Nagano, Y. Nitta, T. Hirayama, Noriyuki Fukushima

引用次数: 146

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine 一种45nm 6b/cell电荷捕获闪存，采用基于ldpc的ECC和漂移免疫软测量引擎

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487709

Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang

{"title":"A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine","authors":"Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang","doi":"10.1109/ISSCC.2013.6487709","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487709","url":null,"abstract":"To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing level when Ni, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"53 1","pages":"222-223"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88625685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

A 95fJ/b current-mode transceiver for 10mm on-chip interconnect 95fJ/b电流模式收发器，用于10mm片上互连

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487727

Seon-Kyoo Lee, Seung-Hun Lee, D. Sylvester, D. Blaauw, J. Sim

{"title":"A 95fJ/b current-mode transceiver for 10mm on-chip interconnect","authors":"Seon-Kyoo Lee, Seung-Hun Lee, D. Sylvester, D. Blaauw, J. Sim","doi":"10.1109/ISSCC.2013.6487727","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487727","url":null,"abstract":"Data communication between local system blocks through on-chip global interconnects presents significant design challenges in scaled VLSI systems. The goal of this research is to reduce the energy consumed per bit transmitted, while achieving Gb/s data rates over interconnect lengths up to 10mm. Voltage-mode signaling with capacitive boosting [1-2] has been proposed for low-power on-chip interconnects. To increase the data rate over RC-limited interconnect, aggressive equalization schemes should be used in receivers [1-3] and transmitters [1-2] at the cost of significant power consumption. As an alternative to voltage-mode signaling, current-mode signaling has been considered. It was originally used for fast bitline sensing in memory [4-5] to take inherent advantage of a reduced RC time constant. However, prior work on current-mode transceivers for on-chip interconnect shows worse energy efficiency than their voltage-mode counterparts due to large static power dissipation by current-sensing circuit [6-7]. This paper presents a 95fJ/b current-mode transceiver for on-chip global interconnect. The transceiver is implemented in 65nm CMOS and achieves a data rate of up to 4Gb/s over a 10mm link with a BER of less than 10-12.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"32 1","pages":"262-263"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88673648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS 采用32nm SOI CMOS的具有基频压控振荡器的210GHz完全集成差分收发器

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487670

Z. Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, P. Heydari

引用次数: 47

A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty 在0.13µm BiCMOS中实现四路25Gb/s 270mW TIA，串扰损耗<0.15dB

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487661

G. Kalogerakis, T. Moran, Thelinh Nguyen, Gilles Denoyer

引用次数: 27

An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency 用于HSUPA发射机的交流耦合混合包络调制器，调制器效率为80%

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487771

P. Riehl, P. Fowers, Hao-Ping Hong, Michael Ashburn

{"title":"An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency","authors":"P. Riehl, P. Fowers, Hao-Ping Hong, Michael Ashburn","doi":"10.1109/ISSCC.2013.6487771","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487771","url":null,"abstract":"High-data-rate wireless technologies such as HSUPA and LTE are power-hungry because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply voltage of the PA must be high enough to provide the peak output voltage without loss of linearity. Envelope tracking modulators have been proposed to improve the efficiency and linearity of transmitters. Modulators using multiple input voltages have been shown to improve efficiency, but generating multiple supplies imposes substantial overhead. Several recent works have demonstrated a hybrid modulator, combining the output current of a buck output stage with that of a linear amplifier. The hybrid modulator has the notable advantage that the low-frequency power (which constitutes the majority of power, even in high-PAPR scenarios) can be provided through the efficient buck stage. The inherently less efficient linear amplifier stage needs only to supply the high-frequency power. The efficiency of hybrid modulators degrades at moderate power levels, when the ac amplitude is much less than the supply voltage of the linear amplifier. At low power levels, the power savings afforded by the modulator do not offset its own quiescent current, resulting in a lower efficiency than can be achieved using a fixed-drain, average-power-tracking (FD-APT) supply.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"8 1","pages":"364-365"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84569858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

A phase-noise and spur filtering technique using reciprocal-mixing cancellation 一种利用互混抵消的相位噪声和杂散滤波技术

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487648

M. Mikhemar, D. Murphy, A. Mirzaei, H. Darabi

{"title":"A phase-noise and spur filtering technique using reciprocal-mixing cancellation","authors":"M. Mikhemar, D. Murphy, A. Mirzaei, H. Darabi","doi":"10.1109/ISSCC.2013.6487648","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487648","url":null,"abstract":"Recent passive-mixer-based architectures, such as [1], have shown that blockers as large as 0dBm can be tolerated without excessive gain compression. However, even in a perfectly linear receiver, reciprocal mixing of the blocker with LO phase noise deposits additive noise on the wanted signal, as shown in Fig. 5.3.1. This is an inevitable limitation to any mixer-based receiver. Assuming that the blocker experiences no passive RF filtering, the noise figure of such a receiver in the presence of a given blocker is only lowered through improving the LO phase noise. To overcome this challenge, most wireless receivers use LC-oscillators that despite their superior phase noise to ring oscillators [2], still consume a large portion of the radio power. As the quality factor of on-chip resonators does not scale with technology, the phase noise of an LC-oscillator can only be improved by consuming more power, while the benefits of circuit innovation are fundamentally limited [3]. Although increasing current helps, it does come at a cost, and is ultimately limited by the maximum allowable amplitude, and how reliably small inductor values can be fabricated without Q-degradation. In this paper, we propose a mixed-signal reciprocal-mixing cancellation technique that leads to a substantial reciprocal-mixing noise figure improvement independent of the LO phase noise.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"20 1","pages":"86-87"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81577811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A 4b ADC manufactured in a fully-printed organic complementary technology including resistors 采用全印刷有机互补技术制造的4b ADC，包括电阻器

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487657

Sahel Abdinia, M. Benwadih, R. Coppard, S. Jacob, G. Maiellaro, G. Palmisano, M. Rizzo, A. Scuderi, F. Tramontana, A. Roermund, E. Cantatore

引用次数: 49

Continuing to shrink: Next-generation lithography - Progress and prospects 继续缩小:新一代光刻技术-进展与前景

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487620

M. V. D. Brink

引用次数: 7