2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers最新文献_第10页

A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer 一种基于非均匀量化器的0.5V <4µW CMOS光容积脉搏波心率传感器IC

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487780

M. Alhawari, Nadya Albelooshi, M. Perrott

{"title":"A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer","authors":"M. Alhawari, Nadya Albelooshi, M. Perrott","doi":"10.1109/ISSCC.2013.6487780","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487780","url":null,"abstract":"Photoplethysmographic biosensing has been of recent interest, since it provides electrode-free operation for continuous health-monitoring applications. This paper presents a <;4μW heart-rate (HR) monitor IC based on measurement of fluctuations in the light intensity passing through tissue such as a finger. As shown in Fig. 22.3.1, key components of the system include a logarithmic, digital-to-resistance converter (DRC) that forms the load of an external photodiode, and a non-uniform quantizer that provides error information to a digital accumulator controlling the DRC input. As the photodiode current fluctuates due to HR-induced pulsing of bloodflow through the tissue, the feedback loop adjusts the DRC load resistance in order to maintain constant voltage across the photodiode. As such, the accumulator output, OUTADC[k], provides a digital representation of HR-induced fluctuations of the photodiode current, and the logarithmic implementation of the DRC accommodates 3 orders of magnitude in light intensity. In order to obtain instantaneous HR frequency, HR[k], off-chip digital signal processing is performed on OUTADC[k].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82896140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A [10°C; 70°C] 640×480 17µm pixel pitch TEC-less IR bolometer imager with below 50mK and below 4V power supply 一个[10°C;70°C] 640×480 17µm像素间距TEC-less红外热辐射计成像仪，低于50mK，低于4V电源

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487785

B. Dupont, A. Dupret, S. Becker, A. Hamelin, F. Guellec, P. Imperinetti, W. Rabaud

引用次数: 19

A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offset 6.3µw20b增量变焦adc, INL为6ppm，偏移量为1µV

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487733

Youngcheol Chae, K. Souri, K. Makinwa

引用次数: 16

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider 带有多输出Bang-Bang鉴相器和基于相位插值器的分数n分频器的2.4 pprs抖动数字锁相环

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487768

R. Nonis, W. Grollitsch, Thomas Santa, Dmytro Cherniak, N. D. Dalt

引用次数: 12

A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits 0.022mm2 970µW双环注入锁相环，−243dB FOM，采用可合成全数字PVT校准电路

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487720

W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, A. Matsuzawa

{"title":"A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits","authors":"W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, A. Matsuzawa","doi":"10.1109/ISSCC.2013.6487720","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487720","url":null,"abstract":"For modern SoC systems, stringent requirements on on-chip clock generators include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [1-2], subharmonically injection-locked techniques [3], and sub-sampling techniques [4-5] can significantly improve the random jitter characteristics of a clock generator. However, in order to guarantee their correct operation and optimal performance over process-voltage-temperature (PVT) variations, each method requires additional calibration circuits, which impose difficult-to-meet timing constraints. In the case of an injection-locked PLL (IL-PLL), a free-running frequency calibration is required. However, the output of an injection-locked oscillator is always fixed at the desired frequency, so a shift in the free-running frequency (e.g. caused by temperature and voltage variations) cannot be simply compensated for by using a frequency-locked loop (FLL). Therefore, we propose the use of a dual-loop topology with one free-running voltage-controlled oscillator (VCO) as a replica VCO placed inside a FLL for tracking temperature and voltage drift. The other VCO (the main VCO) is injection locked for producing a low-jitter clock, while the free-running frequency shift can be compensated for by the replica loop. The method provides robust output over temperature and voltage variations.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74194231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface 一种自适应带宽锁相环，可用于10Gb/s/引脚以上的图形DRAM接口，避免噪声干扰和无dfe快速预充采样

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487749

Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim

{"title":"An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface","authors":"Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim","doi":"10.1109/ISSCC.2013.6487749","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487749","url":null,"abstract":"DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the CIO, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74418099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs 一种用于移动有源矩阵lcd的5.6mV无失配开关电容插补通道间DVO 10b列驱动IC

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487784

Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, S. Ryu, G. Cho

{"title":"A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs","authors":"Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, S. Ryu, G. Cho","doi":"10.1109/ISSCC.2013.6487784","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487784","url":null,"abstract":"To achieve high image quality in mobile active-matrix LCDs, higher DAC resolution and good channel-to-channel uniformity are required in column-driver ICs. In conventional column-driver ICs, the resistor-DAC (R-DAC) architecture has been generally used due to its uniform characteristic, because each R-DAC in driver channels shares a common resistor string for gamma reference-voltage generation. Furthermore, nonlinear gamma correction can be easily implemented using a nonlinear resistor-string that has an inverse transfer curve to the liquid crystal (LC) response. However, the increase in color depth for LCDs results in a large chip-size overhead, thus disclosing the limitation of the R-DAC architecture. To overcome this issue, several hybrid DAC architectures composed of a main 6b R-DAC and a 4b sub-DAC with various interpolation schemes have been reported [1-5]. Their linear interpolation schemes reduce the driver channel size. Meanwhile, their linear 4b interpolation leads to the loss of effective bit resolution for nonlinear gamma correction. In addition, the inevitable mismatch between respective sub-DACs has a significant influence on the channel-to-channel uniform performance of a column-driver IC. In this paper, we present a 10b column-driver IC with a mismatch-free switched-capacitor (SC) interpolation scheme for mobile AMLCDs. The proposed mismatch-free interpolation scheme provides further reduction of the driver size, good linearity, highly uniform channel performance, and more effective bit resolution.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77760613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offset 多径斩波稳定电容耦合运算放大器，输入共模范围为20v，偏移量为3µV

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487688

Qinwen Fan, J. Huijsing, K. Makinwa

{"title":"A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offset","authors":"Qinwen Fan, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2013.6487688","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487688","url":null,"abstract":"Capacitively coupled chopper amplifiers are capable of handling common-mode voltages outside their supply rails, while also achieving high power efficiency and low offset [1-3]. However, a significant drawback of such amplifiers is a transfer-function notch around the chopping frequency (fchop). This is because their input choppers demodulate signals near fchop to DC, where they are blocked by the input capacitors. This problem is exacerbated by the use of a ripple-reduction loop (RRL) to suppress chopper ripple, which also creates a notch at fchop, and, moreover, can take up to 1ms to settle. The net result is an amplifier with a transfer-function notch and a step response that is accompanied by a slowly-decaying burst of chopper ripple [1]. To solve these problems, a multi-path capacitively-coupled chopper-stabilized operational amplifier (MCCOPA) is proposed. Implemented in a HV CMOS 0.7μm technology, it has a smooth transfer function and achieves a 20V common-mode voltage range (CMVR), 3μV offset and 148dB DC CMRR while drawing only 8μA from a 5V supply.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78095582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiency 一种用于光伏组件集成移动器件的自适应负载线调谐IC，具有470µs瞬态时间，超过99%的稳态精度和94%的功率转换效率

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487641

Wen-Chuen Liu, Yi-Hsiang Wang, T. Kuo

引用次数: 17

“Smart life solutions” from home to city 从家到城市的“智慧生活解决方案”

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI: 10.1109/ISSCC.2013.6487619

Yoshiyuki Miyabe

引用次数: 3