A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider

Abstract

In the field of digital PLLs, there is a trend to find alternatives to time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive for their low-jitter, low-power capabilities, but are limited to integer-N operation by nature. Solutions that merge the key performance of the bang-bang architecture with fractional-N operation as in [3] are needed in order to turn the bang-bang digital PLLs into real alternatives to TDC-based PLLs.