2007 25th International Conference on Computer Design最新文献_第7页

Cache replacement based on reuse-distance prediction 基于重用距离预测的缓存替换

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601909

G. Keramidas, Pavlos Petoumenos, S. Kaxiras

引用次数: 128

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros 基于硬宏的片内FPGA异步接口

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601950

Julian J. H. Pontes, R. Soares, Ewerson Carvalho, F. Moraes, Ney Laert Vilar Calazans

引用次数: 38

Accurate modeling and fault simulation of Byzantine resistive bridges 拜占庭式电阻桥的精确建模与故障仿真

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601923

H. Cheung, S. Gupta

引用次数: 4

VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication VIZOR:用于超低功耗无线通信的几乎零边际自适应射频

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601956

R. Senguttuvan, Shreyas Sen, A. Chatterjee

引用次数: 25

Negative-skewed shadow registers for at-speed delay variation characterization 高速延迟变化特性的负偏斜阴影寄存器

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601924

Jie Li, J. Lach

引用次数: 24

A radix-10 SRT divider based on alternative BCD codings 基于备选BCD编码的基数-10 SRT除法器

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601914

Álvaro Vázquez, E. Antelo, P. Montuschi

引用次数: 29

Exploring the interplay of yield, area, and performance in processor caches 探索处理器缓存的产量、面积和性能之间的相互作用

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601905

Hyunjin Lee, Sangyeun Cho, B. Childers

引用次数: 14

FPGA routing architecture analysis under variations FPGA路由结构变化分析

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601894

S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan

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引用次数: 1

Power reduction of chip multi-processors using shared resource control cooperating with DVFS 利用共享资源控制与DVFS合作降低芯片多处理器功耗

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601961

Ryoma Watanabe, Masaaki Kondo, Hiroshi Nakamura, T. Nanya

{"title":"Power reduction of chip multi-processors using shared resource control cooperating with DVFS","authors":"Ryoma Watanabe, Masaaki Kondo, Hiroshi Nakamura, T. Nanya","doi":"10.1109/ICCD.2007.4601961","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601961","url":null,"abstract":"This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can be reduced without violating real-time constraints by dynamic voltage and frequency scaling (DVFS), the clock frequency of each PU cannot be determined independently because of the performance impact caused by the conflict for the shared resources. To minimize power consumption in this situation, we first derive an analytical model which provides the optimal priority and clock frequency setting, and then propose a method of controlling the priority of shared resource accesses in cooperation with DVFS. From the analytical model, in dual-core CMPs, we reveal that the total power consumption is minimized when the clock frequency of two PUs becomes the same. An experiment with a synthetic benchmark supports the validity of the analytical model and the evaluation results with real applications show that the proposed method reduces the power consumption by up to 15% and 6.7% on average compared with a conventional DVFS technique.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"96 1","pages":"615-622"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86609224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Constraint satisfaction in incremental placement with application to performance optimization under power constraints 在功率约束下的性能优化应用中，增量布局的约束满足

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601910

Huan Ren, S. Dutt

{"title":"Constraint satisfaction in incremental placement with application to performance optimization under power constraints","authors":"Huan Ren, S. Dutt","doi":"10.1109/ICCD.2007.4601910","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601910","url":null,"abstract":"We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian relaxation (LR) type approach in the analytical global placement stage to solve the constrained optimization problem. We establish theoretical results that prove the optimality of this stage. In the detailed placement stage, we develop a constraint-monitoring and satisfaction mechanism in a network (n/w) flow based detailed placement framework proposed recently, and empirically show its near-optimality. We establish the effectiveness of our general constraint-satisfaction methods by applying them to the problem of timing-driven optimization under power constraints. We overlay our algorithms on a recently developed unconstrained timing-driven incremental placement method flow-place. On a large number of benchmarks with up to 210K cells, our constraint satisfaction algorithms obtain an average timing improvement of 12.4% under a 3% power increase limit (the actual average power increase incurred is only 2.1%), while the original unconstrained method gives an average power increase of 8.4% for a timing improvement of 17.3%. Our techniques thus yield a tradeoff of 75% power improvement to 28% timing deterioration for the given constraint. Our constraint-satisfying incremental placer is also quite fast, e.g., its run time for the 210 K-cell circuit ibm18 is only 1541 secs.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"66 1","pages":"251-258"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79532801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2