Power reduction of chip multi-processors using shared resource control cooperating with DVFS

Ryoma Watanabe, Masaaki Kondo, Hiroshi Nakamura, T. Nanya
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引用次数: 8

Abstract

This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can be reduced without violating real-time constraints by dynamic voltage and frequency scaling (DVFS), the clock frequency of each PU cannot be determined independently because of the performance impact caused by the conflict for the shared resources. To minimize power consumption in this situation, we first derive an analytical model which provides the optimal priority and clock frequency setting, and then propose a method of controlling the priority of shared resource accesses in cooperation with DVFS. From the analytical model, in dual-core CMPs, we reveal that the total power consumption is minimized when the clock frequency of two PUs becomes the same. An experiment with a synthetic benchmark supports the validity of the analytical model and the evaluation results with real applications show that the proposed method reduces the power consumption by up to 15% and 6.7% on average compared with a conventional DVFS technique.
利用共享资源控制与DVFS合作降低芯片多处理器功耗
本文提出了一种基于实时约束的芯片多处理器(cmp)功耗降低方法。动态电压和频率缩放(DVFS)可以在不违反实时约束的情况下降低cmp上处理器(PU)的功耗,但由于共享资源的冲突会影响性能,因此无法独立确定每个PU的时钟频率。为了在这种情况下最大限度地降低功耗,我们首先推导了一个提供最优优先级和时钟频率设置的分析模型,然后提出了一种与DVFS合作控制共享资源访问优先级的方法。从分析模型来看,在双核cmp中,我们发现当两个pu的时钟频率相同时,总功耗最小。综合基准实验验证了分析模型的有效性,实际应用的评价结果表明,与传统的DVFS技术相比,该方法的功耗平均降低了15%和6.7%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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