ACM Journal on Emerging Technologies in Computing Systems最新文献_第6页

Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT Eternal thing 2.0：用于可持续物联网的模拟特洛伊木马弹性无波纹太阳能采集系统

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-12 DOI: 10.1145/3575800

S. K. Ram, S. Sahoo, B. B. Das, K. Mahapatra, S. Mohanty

{"title":"Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT","authors":"S. K. Ram, S. Sahoo, B. B. Das, K. Mahapatra, S. Mohanty","doi":"10.1145/3575800","DOIUrl":"https://doi.org/10.1145/3575800","url":null,"abstract":"Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3–3.55 V with an input 1–1.5 V with a power throughput of 0–22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"19 1","pages":"1 - 25"},"PeriodicalIF":2.2,"publicationDate":"2022-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41490762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA 基于FPGA的码后量子密码系统密钥生成器的可靠构造

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3544921

Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh

{"title":"Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA","authors":"Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh","doi":"https://dl.acm.org/doi/10.1145/3544921","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3544921","url":null,"abstract":"Advances in quantum computing have urged the need for cryptographic algorithms that are low-power, low-energy, and secure against attacks that can be potentially enabled. For this post-quantum age, different solutions have been studied. Code-based cryptography is one feasible solution whose hardware architectures have become the focus of research in the NIST standardization process and has been advanced to the final round (to be concluded by 2022–2024). Nevertheless, although these constructions, e.g., McEliece and Niederreiter public key cryptography, have strong error correction properties, previous studies have proved the vulnerability of their hardware implementations against faults product of the environment and intentional faults, i.e., differential fault analysis. It is previously shown that depending on the codes used, i.e., classical or reduced (using either quasi-dyadic Goppa codes or quasi-cyclic alternant codes), flaws in error detection could be observed. In this work, efficient fault detection constructions are proposed for the first time to account for such shortcomings. Such schemes are based on regular parity, interleaved parity, and two different cyclic redundancy checks (CRC), i.e., CRC-2 and CRC-8. Without losing the generality, we experiment on the McEliece variant, noting that the presented schemes can be used for other code-based cryptosystems. We perform error detection capability assessments and implementations on field-programmable gate array Kintex-7 device xc7k70tfbv676-1 to verify the practicality of the presented approaches. To demonstrate the appropriateness for constrained embedded systems, the performance degradation and overheads of the presented schemes are assessed.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"28 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2022-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138543453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing 利用串扰计算的嵌入式内存逻辑新方法

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3569917

Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman

{"title":"A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing","authors":"Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman","doi":"https://dl.acm.org/doi/10.1145/3569917","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3569917","url":null,"abstract":"One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"100 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2022-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138505865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AccHashtag: Accelerated Hashing for Detecting Fault-Injection Attacks on Embedded Neural Networks 用于检测嵌入式神经网络故障注入攻击的加速哈希算法

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3555808

Mojan Javaheripi, Jung-Woo Chang, Farinaz Koushanfar

{"title":"AccHashtag: Accelerated Hashing for Detecting Fault-Injection Attacks on Embedded Neural Networks","authors":"Mojan Javaheripi, Jung-Woo Chang, Farinaz Koushanfar","doi":"https://dl.acm.org/doi/10.1145/3555808","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3555808","url":null,"abstract":"We propose AccHashtag, the first framework for high-accuracy detection of fault-injection attacks on Deep Neural Networks (DNNs) with provable bounds on detection performance. Recent literature in fault-injection attacks shows the severe DNN accuracy degradation caused by bit flips. In this scenario, the attacker changes a few DNN weight bits during execution by injecting faults to the dynamic random-access memory (DRAM). To detect bit flips, AccHashtag extracts a unique signature from the benign DNN prior to deployment. The signature is used to validate the model’s integrity and verify the inference output on the fly. We propose a novel sensitivity analysis that identifies the most vulnerable DNN layers to the fault-injection attack. The DNN signature is constructed by encoding the weights in vulnerable layers using a low-collision hash function. During DNN inference, new hashes are extracted from the target layers and compared against the ground-truth signatures. AccHashtag incorporates a lightweight methodology that allows for real-time fault detection on embedded platforms. We devise a specialized compute core for AccHashtag on field-programmable gate arrays (FPGAs) to facilitate online hash generation in parallel to DNN execution. Extensive evaluations with the state-of-the-art bit-flip attack on various DNNs demonstrate the competitive advantage of AccHashtag in terms of both attack detection and execution overhead.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"94 2","pages":""},"PeriodicalIF":2.2,"publicationDate":"2022-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138505887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

B-open Defect: A Novel Defect Model in FinFET Technology b开缺陷:一种新型的FinFET技术缺陷模型

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3564244

Freddy Forero, Victor Champac, Michel Renovell

引用次数: 0

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3568957

Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata

{"title":"Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis","authors":"Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata","doi":"https://dl.acm.org/doi/10.1145/3568957","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3568957","url":null,"abstract":"Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 μm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"99 2","pages":""},"PeriodicalIF":2.2,"publicationDate":"2022-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138505868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Taming Molecular Field-Coupling for Nanocomputing Design 纳米计算设计中的分子场耦合控制

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-09 DOI: https://dl.acm.org/doi/10.1145/3552520

Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano

{"title":"Taming Molecular Field-Coupling for Nanocomputing Design","authors":"Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano","doi":"https://dl.acm.org/doi/10.1145/3552520","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3552520","url":null,"abstract":"Molecular Field-Coupling Nanocomputing (FCN) is one of the most promising technologies for overcoming Complementary Metal Oxide Semiconductor (CMOS) scaling issues. It encodes the information in the charge distribution of nanometric molecules and propagates it through local electrostatic intermolecular interaction. This technology promises very high speed at ambient temperatures with minimal power dissipation. The main research focus on molecular FCN is currently either on single-molecule low-level analysis or circuit design based on naïve assumptions. We aim to fill this gap, assessing the potential and feasibility of FCN. We present a bottom-up analysis and design framework that starts from the physical characterization of molecular and technological parameters and enables physical-aware FCN designs. The framework explicitly considers molecular physics, allowing the designer to tame the molecular interaction to ensure the computational capabilities of the final device. The framework permits studying possible physical effects that create cross-implications and correlations among physical and system-level layers considering possible behavior variability. We characterize and verify molecular propagation in increasingly structured layouts to design complex arithmetic circuits. The results highlight molecular FCN advantages, especially in area occupation, and provide valuable quantitative feedback to designers and technologists to support the assessment of molecular FCN and the realization of an eventual prototype.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"93 3","pages":""},"PeriodicalIF":2.2,"publicationDate":"2022-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138505889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automated Generation of Security Assertions for RTL Models RTL模型安全断言的自动生成

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-11-22 DOI: 10.1145/3565801

Hasini Witharana, Aruna Jayasena, Andrew Whigham, P. Mishra

{"title":"Automated Generation of Security Assertions for RTL Models","authors":"Hasini Witharana, Aruna Jayasena, Andrew Whigham, P. Mishra","doi":"10.1145/3565801","DOIUrl":"https://doi.org/10.1145/3565801","url":null,"abstract":"System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is widely used for functional validation of Register-Transfer Level (RTL) designs. Assertions can improve the controllability and observability that can lead to faster error detection and localization. Although assertions are widely used for functional validation of RTL models, there is limited effort in applying assertions to detect SoC security vulnerabilities. Specifically, a fundamental challenge in SoC security and trust validation is how to develop high-quality security assertions. In this article, we perform automated vulnerability analysis of RTL models to generate security assertions for six classes of vulnerabilities. Experimental results show that the generated security assertions can detect a wide variety of vulnerabilities. Our automated framework can drastically reduce the overall security validation effort compared to the manual development of security assertions. Automated generation of security assertions will enable assertion-based verification to be one of the most promising pre-silicon security sign-off solutions.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"19 1","pages":"1 - 27"},"PeriodicalIF":2.2,"publicationDate":"2022-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43563836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs 2DMAC：一种适用于未来无线节点的可持续高效的介质访问控制机制

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-11-05 DOI: 10.1145/3570727

Sidhartha Sankar Rout, Mitali Sinha, Sujay Deb

{"title":"2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs","authors":"Sidhartha Sankar Rout, Mitali Sinha, Sujay Deb","doi":"10.1145/3570727","DOIUrl":"https://doi.org/10.1145/3570727","url":null,"abstract":"Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due to the varying traffic density across the WNoC. Moreover, the conventional WNoCs give equal importance to all the traffic taking the wireless path and transmit it in an oldest-first manner. Nevertheless, the critical data can degrade the system performance to a large extent by delaying the application runtime if not served promptly. We propose 2DMAC, which can change the token arbitration pattern and tune the channel hold time of each WI based on its runtime traffic density and criticality status. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer. The proposed mechanism improves the wireless channel utilization by 15.67% and the network throughput by 29.83% and reduces the critical data latency by 29.77% over the traditional MAC.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":" ","pages":"1 - 25"},"PeriodicalIF":2.2,"publicationDate":"2022-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47686505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing 利用串扰计算的嵌入式内存逻辑新方法

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-11-01 DOI: 10.1145/3569917

Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman

{"title":"A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing","authors":"Prerana Samant, Naveen Kumar Macha, Mostafizur Rahman","doi":"10.1145/3569917","DOIUrl":"https://doi.org/10.1145/3569917","url":null,"abstract":"One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"19 1","pages":"1 - 16"},"PeriodicalIF":2.2,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46776367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0