ACM Journal on Emerging Technologies in Computing Systems最新文献_第5页

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle 安全CAD特刊简介:设计周期内的预硅安全签署解决方案

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-03-17 DOI: https://dl.acm.org/doi/10.1145/3584317

Farimah Farahmandi, Ankur Srivastava, Giorgio Di Natale, Mark Tehranipoor

引用次数: 0

Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware 基于时序的软件侧信道攻击特征及片上网络硬件的缓解

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-03-02 DOI: 10.1145/3585519

U. Ali, Sheikh Abdul Rasheed Sahni, O. Khan

{"title":"Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware","authors":"U. Ali, Sheikh Abdul Rasheed Sahni, O. Khan","doi":"10.1145/3585519","DOIUrl":"https://doi.org/10.1145/3585519","url":null,"abstract":"Modern network-on-chip (NoC) hardware is an emerging target for side-channel security attacks. A recent work implemented and characterized timing-based software side-channel attacks that target NoC hardware on a real multicore machine. This article studies the impact of system noise on prior attack setups and shows that high noise is sufficient to defeat the attacker. We propose an information theory-based attack setup that uses repetition codes and differential signaling techniques to de-noise the unwanted noise from the NoC channel to successfully implement a practical covert-communication attack on a real multicore machine. The evaluation demonstrates an attack efficacy of 97%, 88%, and 78% under low, medium, and high external noise, respectively. Our attack characterization reveals that noise-based mitigation schemes are inadequate to prevent practical covert communication, and thus isolation-based mitigation schemes must be considered to ensure strong security. Isolation-based schemes are shown to mitigate timing-based side-channel attacks. However, their impact on the performance of real-world security critical workloads is not well understood in the literature. This article evaluates the performance implications of state-of-the-art spatial and temporal isolation schemes. The performance impact is shown to range from 2–3% for a set of graph and machine learning workloads, thus making isolation-based mitigations practical.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":" ","pages":"1 - 23"},"PeriodicalIF":2.2,"publicationDate":"2023-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49039123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Mapping Method Tolerating SAF and Variation for Memristor Crossbar Array Based Neural Network Inference on Edge Devices 边缘器件上基于神经网络推理的忆阻器横条阵列容SAF和变异映射方法

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-02-25 DOI: 10.1145/3585518

Yu Ma, Linfeng Zheng, Pingqiang Zhou

{"title":"A Mapping Method Tolerating SAF and Variation for Memristor Crossbar Array Based Neural Network Inference on Edge Devices","authors":"Yu Ma, Linfeng Zheng, Pingqiang Zhou","doi":"10.1145/3585518","DOIUrl":"https://doi.org/10.1145/3585518","url":null,"abstract":"There is an increasing demand for running neural network inference on edge devices. Memristor crossbar array (MCA) based accelerators can be used to accelerate neural networks on edge devices. However, reliability issues in memristors, such as stuck-at faults (SAF) and variations, lead to weight deviation of neural networks and therefore have a severe influence on inference accuracy. In this work, we focus on the reliability issues in memristors for edge devices. We formulate the reliability problem as a 0–1 programming problem, based on the analysis of sum weight variation (SWV). In order to solve the problem, we simplify the problem with an approximation - different columns have the same weights, based on our observation of the weight distribution. Then we propose an effective mapping method to solve the simplified problem. We evaluate our proposed method with two neural network applications on two datasets. The experimental results on the classification application show that our proposed method can recover 95% accuracy considering SAF defects and can increase by up to 60% accuracy with variation σ =0.4. The results of the neural rendering application show that our proposed method can prevent render quality reduction.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"19 1","pages":"1 - 21"},"PeriodicalIF":2.2,"publicationDate":"2023-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42933281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-02-17 DOI: 10.1145/3584183

Mingdai Yang, Qiuwen Lou, R. Rajaei, M. Jokar, Junyi Qiu, Yuming Liu, Aditi Udupa, F. Chong, J. Dallesasse, Milton Feng, L. Goddard, X. S. Hu, Yanjing Li

{"title":"A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals","authors":"Mingdai Yang, Qiuwen Lou, R. Rajaei, M. Jokar, Junyi Qiu, Yuming Liu, Aditi Udupa, F. Chong, J. Dallesasse, Milton Feng, L. Goddard, X. S. Hu, Yanjing Li","doi":"10.1145/3584183","DOIUrl":"https://doi.org/10.1145/3584183","url":null,"abstract":"Optical deep learning (DL) accelerators have attracted significant interests due to their latency and power advantages. In this article, we focus on incoherent optical designs. A significant challenge is that there is no known solution to perform single-wavelength accumulation (a key operation required for DL workloads) using incoherent optical signals efficiently. Therefore, we devise a hybrid approach, where accumulation is done in the electrical domain, and multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently. Through detailed design and evaluation of our design, along with a comprehensive benchmarking study against state-of-the-art RRAM-based designs, we derive the following key results: (1) For a four-layer multilayer perceptron network, our design achieves 115× and 17.11× improvements in latency and energy, respectively, compared to the RRAM-based design. We can take full advantage of the speed and energy benefits of the optical technology because the inference task can be entirely mapped onto our design. (2) For a complex workload (Resnet50), weight reprogramming is needed, and intermediate results need to be stored/re-fetched to/from memories. In this case, for the same area, our design still outperforms the RRAM-based design by 15.92× in inference latency, and 8.99× in energy.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":" ","pages":"1 - 24"},"PeriodicalIF":2.2,"publicationDate":"2023-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47917167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle 安全CAD特刊简介：设计周期中的预硅安全签字解决方案

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-01-31 DOI: 10.1145/3584317

Farimah Farahmandi, Ankur Srivastava, Giorgio Di Natale, M. Tehranipoor

引用次数: 0

Survey of Approaches and Techniques for Security Verification of Computer Systems 计算机系统安全验证方法与技术综述

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-01-19 DOI: https://dl.acm.org/doi/10.1145/3564785

Ferhat Erata, Shuwen Deng, Faisal Zaghloul, Wenjie Xiong, Onur Demir, Jakub Szefer

引用次数: 0

Automated Generation of Security Assertions for RTL Models RTL模型安全断言的自动生成

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-01-19 DOI: https://dl.acm.org/doi/10.1145/3565801

Hasini Witharana, Aruna Jayasena, Andrew Whigham, Prabhat Mishra

{"title":"Automated Generation of Security Assertions for RTL Models","authors":"Hasini Witharana, Aruna Jayasena, Andrew Whigham, Prabhat Mishra","doi":"https://dl.acm.org/doi/10.1145/3565801","DOIUrl":"https://doi.org/https://dl.acm.org/doi/10.1145/3565801","url":null,"abstract":"<p>System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is widely used for functional validation of Register-Transfer Level (RTL) designs. Assertions can improve the controllability and observability that can lead to faster error detection and localization. Although assertions are widely used for functional validation of RTL models, there is limited effort in applying assertions to detect SoC security vulnerabilities. Specifically, a fundamental challenge in SoC security and trust validation is how to develop high-quality security assertions. In this article, we perform automated vulnerability analysis of RTL models to generate security assertions for six classes of vulnerabilities. Experimental results show that the generated security assertions can detect a wide variety of vulnerabilities. Our automated framework can drastically reduce the overall security validation effort compared to the manual development of security assertions. Automated generation of security assertions will enable assertion-based verification to be one of the most promising pre-silicon security sign-off solutions.</p>","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"98 4","pages":""},"PeriodicalIF":2.2,"publicationDate":"2023-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138505870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Rank Gradient Descent for Memory-Efficient Training of Deep In-Memory Arrays 基于低秩梯度下降的深度内存数组高效训练

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-01-13 DOI: 10.1145/3577214

Siyuan Huang, B. Hoskins, M. Daniels, M. Stiles, G. Adam

{"title":"Low-Rank Gradient Descent for Memory-Efficient Training of Deep In-Memory Arrays","authors":"Siyuan Huang, B. Hoskins, M. Daniels, M. Stiles, G. Adam","doi":"10.1145/3577214","DOIUrl":"https://doi.org/10.1145/3577214","url":null,"abstract":"The movement of large quantities of data during the training of a deep neural network presents immense challenges for machine learning workloads, especially those based on future functional memories deployed to store network models. As the size of network models begins to vastly outstrip traditional silicon computing resources, functional memories based on flash, resistive switches, magnetic tunnel junctions, and other technologies can store these new ultra-large models. However, new approaches are then needed to minimize hardware overhead, especially on the movement and calculation of gradient information that cannot be efficiently contained in these new memory resources. To do this, we introduce streaming batch principal component analysis (SBPCA) as an update algorithm. Streaming batch principal component analysis uses stochastic power iterations to generate a stochastic rank-k approximation of the network gradient. We demonstrate that the low-rank updates produced by streaming batch principal component analysis can effectively train convolutional neural networks on a variety of common datasets, with performance comparable to standard mini-batch gradient descent. Our approximation is made in an expanded vector form that can efficiently be applied to the rows and columns of crossbars for array-level updates. These results promise improvements in the design of application-specific integrated circuits based around large vector-matrix multiplier memories.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"19 1","pages":"1 - 24"},"PeriodicalIF":2.2,"publicationDate":"2023-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42537203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AroMa: Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators AroMa：评估深度学习系统对多租户加速器的窃取完整性攻击

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2023-01-06 DOI: 10.1145/3579033

Xiangru Chen, Maneesh Merugu, Jiaqi Zhang, Sandip Ray

引用次数: 0

On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective 保护加密ic免受基于扫描的攻击:一个汉明权重分布的观点

IF 2.2 4区计算机科学

ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-12-22 DOI: 10.1145/3577215

Dipojjwal Ray, Yogendra Sao, S. Biswas, Sk Subidh Ali

{"title":"On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective","authors":"Dipojjwal Ray, Yogendra Sao, S. Biswas, Sk Subidh Ali","doi":"10.1145/3577215","DOIUrl":"https://doi.org/10.1145/3577215","url":null,"abstract":"Scan chain-based Design for Testability is the industry standard in use for testing manufacturing defects in the semiconductor industry to ensure the structural and functional correctness of chips. Fault coverage is significantly enhanced due to the higher observability and controllability of the internal latches. These ensuing benefits to testing, if misused, expose vulnerabilities that can be detrimental to the security aspects, especially in the context of crypto-chips that contain a secret key. Hence, it remains of paramount importance for a chip designer to secure crypto-chips against various scan attacks. A countermeasure is proposed in this article that preserves the secrecy of an embedded key in a cryptographic integrated circuit running an Advanced Encryption Standard (AES) implementation. A novel design involving a hardware unit is illustrated that circumvents differential scan attacks by essentially performing bit flips deterministically, using a pre-computed mask value. This helps secure the chip while retaining full testability. The controller logic directly depends on a mask determination algorithm that can defend against any scan attack with 𝒪 theoretical complexity. Security analysis of our proposed defense procedure is performed in the framework of Discrete Event Systems (DES). The sequential scan circuit of an AES cryptosystem is modeled as a DES using Finite State Automata. A security notion, Opacity, is used to quantify and formally verify the security aspects of our controlled system, which shows that the entropy of the secret key is preserved. A case study is performed that shows to mitigate state-of-the-art differential scan attacks successfully at a nominal extra overhead of 1.78%.","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":" ","pages":"1 - 20"},"PeriodicalIF":2.2,"publicationDate":"2022-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46087379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1