IEEE Design & Test of Computers最新文献_第2页

Conference reports 会议报告

IEEE Design & Test of Computers Pub Date : 2016-01-01 DOI: 10.1109/MDT.2004.54

Jorge A. Pérez

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A Tale of Two Technology Disruptions 两种技术颠覆的故事

IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/MDAT.2014.2355093

K. Bergman

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Mr. Synopsys Speaks: The Aart of Tech-Onomic Orchestration of Adjacent Version $n+1$ Synopsys先生演讲:相邻版本的技术编曲艺术$n+1$

IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/MDAT.2014.2349277

E. Marinissen

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Guest Editors' Introduction: Silicon Nanophotonics for Future Multicore Architectures 客座编辑导言:未来多核架构的硅纳米光子学

IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/MDAT.2014.2355512

S. Pasricha, Yi Xu

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Silicon Nanophotonics 硅纳米光子学

IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/mdat.2014.2355391

A. Ivanov

引用次数: 16

The Obligatory Internet-of-Things Column 强制性的物联网专栏

IEEE Design & Test of Computers Pub Date : 2014-08-07 DOI: 10.1109/MDAT.2014.2337234

S. Davidson

{"title":"The Obligatory Internet-of-Things Column","authors":"S. Davidson","doi":"10.1109/MDAT.2014.2337234","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2337234","url":null,"abstract":"h I ARRIVED AT my friend George’s new house as the temperature outside had begun to drop. The place was bigger than I had expected. I rang the doorbell, which played a clip of John Lennon singing ‘‘Money.’’ George opened the door and greeted me. The living room, as usual had one couch, one small table, two chairs, and about a dozen servers. Still, it was impressive. ‘‘How did you score this place?’’ I asked George. Housing in the Bay Area was hot these days. ‘‘I got lucky,’’ George said. ‘‘The guy who owned it before made his money in Alabama, heard about bitcoins, and came here to cash in.’’ George grinned. ‘‘By selling leather-tooled purses for them. It turns out that just like some people don’t want to buy a house where someone died, around here they don’t buy houses where businesses died. Except this is more serious because money is involved.’’ ‘‘So what’s your new big idea?’’ I asked. ‘‘Everyone’s doing Internet-of-Things startups, net-enabling everything from refrigerators to picture frames to thermostats. So I’m doing it too. Just about everything in this house is smart. ‘‘But that’s not enough to differentiate a startup.’’ George continued. ‘‘Then it came to me. If all your appliances talk to one another, it might be a good idea to be able to listen in.’’ I rolled my eyes. ‘‘That’s a bogus idea, even for you,’’ I told him. ‘‘The computer illiterate are sure going to want to look at packet counts.’’ ‘‘You are correct. My system translates the commands into English, and it has an AI to interpret the commands in the context of the house’s environment.’’ George looked at his smart watch. ‘‘You’re just in time to see the heating and cooling system go into action. Follow me.’’ We went into a gigantic room. One wall was lined with windows, all closed and curtained to keep out the afternoon heat. George led me to the interior wall, which had speakers, displays, a thermostat, and what turned out to be a thermometer. ‘‘The thermometer displays temperatures from inside as well as from a bunch of temperature sensors outside. That way the house can figure out the exact time to turn off the air conditioning and open the windows.’’ He pushed a button. ‘‘Let’s listen in.’’ Thermostat: Temperature outside cool enough. Air conditioner off, curtains up, windows, open. AC: Off? It’s stifling in here. Windows: Which way is open? Curtains: If I fold up I get all creased. Thermostat: Windows, open is up. Air conditioner off. AC: I’ll compromise. I’ll set myself up five degrees. Window: Which way is up? Curtains: You see, no one cares about us. We’re just window dressing. Thermostat: Air conditioner off already. Curtains, the iron can smooth you out. Window, up is toward the ceiling. Curtains: Okay. We like Iron. He’s hot. Going up now. Windows: What’s a ceiling? Thermostat: *&*$%$# Just flex. Windows. Flexing. Oh, that open. Thermostat: Air conditioner, set yourself to 99 degrees.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2337234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Bottom Line of Complex ICs and Systems on Chip [From the EIC] 复杂集成电路和片上系统的底线[来自EIC]

IEEE Design & Test of Computers Pub Date : 2014-08-01 DOI: 10.1109/MDAT.2014.2343311

A. Ivanov

{"title":"The Bottom Line of Complex ICs and Systems on Chip [From the EIC]","authors":"A. Ivanov","doi":"10.1109/MDAT.2014.2343311","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2343311","url":null,"abstract":"h THIS ISSUE OF IEEE Design & Test brings to our readers a selection of highly progressive and relevant topics, focusing intently on solutions to some of today’s most challenging areas facing the design, manufacturing, and deployment of complex ICs and systems on chip. The articles highlight advances in yield improvement, design methodologies, testing, diagnosis, and temperature and power management in 3-D ICs and mixed signal circuits. I am again very pleased to present another timely issue on the fringe of our industry’s progression. By reading the articles, as I mention below, they all very much address the bottom line! This usually matters to most if not all of us! Read on! Our first article will be of interest to a broad set of constituents, from designers, to process engineers, to quality assurance personnel, and more. It comes from an international group of authors ranging from Cadence Design Systems, to UCLA and the Missouri University of Science and Technology, to Nanyang Technological University in Singapore. It is a wellknown fact that process variations in deeply scaled technologies create major design and fabrication challenges. Accurately predicting yield for analog and mixed signal circuits is equally challenging but extremely important to the success of a product and company. The article here is focused precisely on yield estimation. The authors present two distinct approaches, one that is referred to as a performance domain method, and a second referred to as a parameter domain method. The authors present a thorough analysis of the tradeoffs of these two approaches through a number of circuit examples and quantitative comparisons of the efficiency of the two different methods. The second article, by a group of Taiwanese authors, moves us back to the emerging world of 3-D ICs and yield. The authors focused their work on the integrity of interconnects in 3-D ICs, which has major impact on yield of such chips. They address design for testability, built-in self-test, and defect diagnosis and repair in 3-D ICs that are based on through silicon vias (TSVs) and interposers. The claimed improvement results are significant and should make a difference to the bottom line! Following this, Bhagavatula et al. from Purdue University present a detailed view of the issues faced in the development and implementation of real-time power sensors that may be the key to successful and cost-effective intelligent power management in highperformance ICs and systems. The authors make the point that the need for accurate on-chip estimation of load currents is critical. They present a proposed solution approach to this challenge and discuss broader issues surrounding power management. Rounding out this general-interest issue, an article by Huang and Huang from the National Tsing Hua University in Taiwan takes us back to a test and yield/binning problem with 3-D TSV ICs. The authors present the usefulness of a cell-based phaselocked loop that can be synthesi","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2343311","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62452207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editors' Introduction: Hardware Acceleration in Computational Biology 客座编辑简介:计算生物学中的硬件加速

IEEE Design & Test of Computers Pub Date : 2014-02-24 DOI: 10.1109/MDAT.2013.2295761

P. Pande, A. Kalyanaraman

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Advanced architecture as a commodity 作为商品的高级架构

IEEE Design & Test of Computers Pub Date : 2014-02-01 DOI: 10.1109/MDAT.2014.2299596

S. Davidson

引用次数: 0

A look at accelerated hardware in computational biology 计算生物学中的加速硬件

IEEE Design & Test of Computers Pub Date : 2014-02-01 DOI: 10.1109/MDAT.2014.2302039

A. Ivanov

{"title":"A look at accelerated hardware in computational biology","authors":"A. Ivanov","doi":"10.1109/MDAT.2014.2302039","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2302039","url":null,"abstract":"Welcome to 2014! h FOLLOWING DECEMBER 2013’S special year end issue on the slowing effects of variability and aging in ICs and systems, to start this new volume of D&T we bring you to a completely different space. In this issue, we take a focused look into the growing computational challenges associated with molecular biology research. The generation of biological data is now happening at unprecedented rates, and processing rates have not really kept pace. Such processing has typically been carried out in software on standard desktop computing platforms, but this situation is changing. This issue explores such changes and highlights some of the hardware-based approaches and corresponding algorithms that have been developed to enable highly desired biological data processing acceleration. Our first article, by Majumder et al., dives into the specifics of high-speed rates of data generation in molecular biology research. The article compares the performance of emerging hardware platforms with other applications across the field of computational biology. Second, an article by Aluru and Jammula provides a wider scope investigation by presenting surveys on FPGA and GPU hardware accelerators in biological sequence analysis, as well as research on acceleration resulting from examining high-throughput sequencing and applications. Our third submission, authored by Liu and Schmidt, presents two critical computing techniques for CUDA-enabled GPUs that allow fast alignments to accelerate the CUSHAW2 algorithm, supported by the alignments of simulated and real reads to the human genome. Next, Schlachter et al. investigate the problem of resource utilization in molecular dynamics simulations. They focus on non-dedicated high-end clusters and propose additional modules to supplement existing workflow and resource managers. They report on two molecular simulations and validate the performance benefits that their proposed approaches bring. Following this, authors Savran, Gao, and Bakos discuss improvements to the memory usage and performance of their GPU kernel, which performs large-scale short sequence dataset pair wise alignments. The authors have established a possible new record in large-scale alignments. To conclude this discussion of computational biology acceleration, an article by Chrysos et al. presents a number of informative case studies that exemplify how modern hybrid systems with FPGAbased reconfigurable computing platforms can offer large speed-ups and savings in bioinformatics algorithms. Our last three feature articles touch on more general interest topics. The first is an article by Yilmaz, Nassery, and Ozev that outlines and confirms the accuracy of built-in EVM measurement techniques that use QAM modulation and avoid high DFT overheads. Following this, Jenihhin et. al present an approach to design error localization that combines statistical analysis of VHDL code items with static slicing. The authors demonstrate the efficiency of their approa","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2302039","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0