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A Tale of Two Technology Disruptions 两种技术颠覆的故事
IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/MDAT.2014.2355093
K. Bergman
{"title":"A Tale of Two Technology Disruptions","authors":"K. Bergman","doi":"10.1109/MDAT.2014.2355093","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2355093","url":null,"abstract":"With power dissipation severely limiting the frequency scaling of microprocessors, the emergence of chip multiprocessors (CMPs) had shifted computingto embrace highly parallel multicore architectures. Realizing performance in these newgenerations of chips is becoming increasingly dependent on how efficiently applications can exploit the growing number of parallel resources. Whereas computation power as measured in FLOPs was the key metric of past microprocessors, performance in today?s CMPs is dominated by data movement challenges. In this so-called ``communications bound?? era of computing, new technologies are sought that can deliver energy-efficient high-bandwidth interconnectivity. While optics is a natural communications technology with broad success in long-haul fiber optic telecommunications, integration at the chip scale, particularly with silicon, had been challenging.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"31 1","pages":"87-88"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2355093","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mr. Synopsys Speaks: The Aart of Tech-Onomic Orchestration of Adjacent Version $n+1$ Synopsys先生演讲:相邻版本的技术编曲艺术$n+1$
IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/MDAT.2014.2349277
E. Marinissen
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引用次数: 0
Silicon Nanophotonics 硅纳米光子学
IEEE Design & Test of Computers Pub Date : 2014-10-01 DOI: 10.1109/mdat.2014.2355391
A. Ivanov
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引用次数: 16
Guest Editors' Introduction: Hardware Acceleration in Computational Biology 客座编辑简介:计算生物学中的硬件加速
IEEE Design & Test of Computers Pub Date : 2014-02-24 DOI: 10.1109/MDAT.2013.2295761
P. Pande, A. Kalyanaraman
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引用次数: 0
ICCAD roundtable the many challenges of triple patterning [ICCAD Roundtable] ICCAD圆桌会议:三重模式的诸多挑战[ICCAD圆桌会议]
IEEE Design & Test of Computers Pub Date : 2014-01-01 DOI: 10.1109/MDAT.2014.2337471
W. Joyner, J. Kawa, L. Liebmann, D. Pan, Martin D. F. Wong, David Yeh
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引用次数: 2
“Our Original 3D Idea Still Has To Happen; And It Will” “我们最初的3D想法仍然需要实现;它会的。”
IEEE Design & Test of Computers Pub Date : 2013-12-19 DOI: 10.1109/MDAT.2013.2286547
E. Marinissen
{"title":"“Our Original 3D Idea Still Has To Happen; And It Will”","authors":"E. Marinissen","doi":"10.1109/MDAT.2013.2286547","DOIUrl":"https://doi.org/10.1109/MDAT.2013.2286547","url":null,"abstract":"Ivo Bolsens is senior vice president (SVP) and chief technology officer (CTO) at Xilinx, a leading supplier of field-programmable gate arrays (FPGAs). At Xilinx, he is responsible for advanced technology development, as well as the company's research laboratories and university program. Design & Test's Erik Jan Marinissen met with Dr. Bolsens in November 2012 during the IEEE International Test Conference in Anaheim, CA,USA, where Bolsens was the opening keynote speaker at the co-located 3D-TEST Workshop . Shortly prior to his keynote talk, this interview took place during lunch at a Disneyland restaurant, covering Bolsens' career from IMEC to Xilinx, current and future FPGAs, the differences between research and company environments, and Xilinx recent 3D-FPGA product.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"30 1","pages":"83-88"},"PeriodicalIF":0.0,"publicationDate":"2013-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2013.2286547","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Look at Variability and Aging 变异与衰老的关系
IEEE Design & Test of Computers Pub Date : 2013-12-01 DOI: 10.1109/MDAT.2014.2298356
A. Ivanov
{"title":"A Look at Variability and Aging","authors":"A. Ivanov","doi":"10.1109/MDAT.2014.2298356","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2298356","url":null,"abstract":"h THE NEED FOR more densely packed, faster and more energy-efficient devices has forced significant evolutions in device architectures in recent years. A challenging byproduct of such trends is increased variability of the performance parameters of manufactured devices and a move towards increased electrical stresses imposed on devices during their field use. In turn, increased electrical stress causes further increases in performance variability over time. In shorter form, two major obstacles arise for modern IC designers: variability and aging. The focus of this special issue is to bring to our attention the need for mediating impacts of variability and aging across the many stages of IC and integrated systems design. Developing innovative, yet feasible solutions for these matters are an urgent concern for future computing systems surging forward on the cusp of innovation. This month we bring you a collection of articles that thoroughly examine how the impacts of variability and aging are seen by experts and can be dealt with. To begin this special-themed issue, a paper by Bowman et al. discusses the effects of variability on microprocessor performance through an analysis of error-detection and recovery circuits, among other circuit types and monitors. An article by Wang et al. then provides a detailed look at the variability and reliability of 6T-SRAM memory systems, to show the criticality of variability effects on SRAM in computing systems. In our third article, Gupta and Roy continue the SRAM focus but specifically regard FinFET technology with a cost-benefit analysis through specific device and circuit co-designmethods. Next, Chen et al. shed light on mitigating strategies to offset NBTI effects in current circuit optimizing methods. We follow this with a paper by Stott et al. that looks at the impacts of variability and aging in FPGAs. This article proposes an adaptive system that can reconfigure its own architecture to counter variability and aging effects. A sixth entry by Debashi and Fey presents the capabilities of using Boolean Satisfiability in automating speedpath debugging under timing variations. We have also included in this final issue of 2013, three general interest articles that step away from our detailed look at variability and aging. The first of the three is an examination by Villacorta et al. of a dominant failuremechanism innanometer technology that of open defects in vias. Results of risk and reliability analyses show that new electromigration design rules are needed in light of resistive vias. The following article, provided by Laraba et al. from the TIMA Laboratory in Grenoble, demonstrates a low-cost digital monitoring alternative in reduced code testing. The last featured article is a contribution from Sayil et al. on transient noise effects caused by single event particles. The authors focus on coupling-induced soft-error mechanisms in combinational logic. We conclude this issue with ‘‘The Last Byte’’ by Scott Dav","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"144 1","pages":"4-4"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2298356","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guest Editors' Introduction: Special Issue on Variability and Aging 特邀编辑导言:变异与衰老特刊
IEEE Design & Test of Computers Pub Date : 2013-12-01 DOI: 10.1109/MDAT.2013.2297040
A. Rubio, Antonio González
{"title":"Guest Editors' Introduction: Special Issue on Variability and Aging","authors":"A. Rubio, Antonio González","doi":"10.1109/MDAT.2013.2297040","DOIUrl":"https://doi.org/10.1109/MDAT.2013.2297040","url":null,"abstract":"The articles in this special section focus on new technological innovationsin EDA design. The constant evolution of electronic systems has been fueled by the continuous and tremendous progress of silicon technology manufacturing. Since 1960, when the first MOS transistor was manufactured with dimensions around 50 cm, process technology has been constantly enhancing until the current 22-nm MOS technology. Every two years a new process generation roughly doubles the device density, following what is known as Moore's law. Besides, every new generation offers faster devices that consume less energy by operation. This has put in the hands of architects more powerful and energy-efficient building blocks on top of which they have designed more effective architectures with increasing capabilities. Silicon MOSFETs have been the workhorse devices for information technologies during all these last decades. However, these technology advances have to deal with important challenges coming from physical limitations of the underlying transistors, which are affected by severe manufacturing process parameters variability and aging caused by electrical degradation of materials due to the intense electrical stress during operation.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"30 1","pages":"5-7"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2013.2297040","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guest Editors' Introduction: Silicon Debug and Diagnosis 客座编辑简介:硅的调试和诊断
IEEE Design & Test of Computers Pub Date : 2013-11-08 DOI: 10.1109/MDAT.2013.2279324
N. Nicolici, B. Benware
{"title":"Guest Editors' Introduction: Silicon Debug and Diagnosis","authors":"N. Nicolici, B. Benware","doi":"10.1109/MDAT.2013.2279324","DOIUrl":"https://doi.org/10.1109/MDAT.2013.2279324","url":null,"abstract":"h TROUBLESHOOTING HOW AND why circuits and systems fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for research and development, or just getting a working first prototype. This detective work is, however, very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle, and time to market. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity. This special section of IEEE Design & Test includes the extended versions of the three best contributions presented at the Silicon Debug and Diagnosis (SDD) Workshop, which was held in Anaheim, CA, USA, in November 2012. It was the eighth of a series of highly successful technical workshops that consider issues related to debug and diagnosis of semiconductor circuits and systems: from prototype bring-up to volume production. The first paper, ‘‘Linking the verification and validation of complex integrated circuits through shared coverage metrics’’ by Hung et al., discusses how to bridge pre-implementation (commonly referred to also as ‘‘pre-silicon’’) verification to postimplementation validation in an emulation environment. Considering the inherent flexibility offered by field-programmable gate arrays (FPGAs), the authors discuss howembedded instrumentation can aiddata acquisition and coverage measurement in FPGA designs. The evolution of FPGA trace collection methods is elaborated, showing how recent tools can facilitate a set of predetermined cover points to be observed without requiring recompilation. Further, recent research is aimed at enabling any cover point to be measured in FPGA prototypes. In the second paper, entitled ‘‘Evolution of graphics Northbridge test and debug architectures across four generations of AMD ASICs,’’ Margulis et al., present the evolution of the design for test and debug (commonly referred to as DFx) architectures over four generations of AMD designs. The paper covers different aspects of DFx, ranging from scan architecture to control (centralized, modular, hierarchical) to debug buses (asynchronous/synchronous, source synchronous). The key points are that DFx methodology must be physical-design friendly and account for high clock frequencies, needed to acquire and dump the trace data, as well as be aware of the power savings features, such clock and power gating. In the last paper of this special section, entitled ‘‘Deriving feature fail rate from silicon volume diagnostics data,’’ Malik et al., address the challenge of identifying layout geometries that lead to systematic yield loss. As the subwavelength lithography gap continues to widen, this class of defect is becoming an increasingly dominant source of failures. With design-for-manufacturability (DFM) tools, it is possible to identify pot","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"30 1","pages":"6-7"},"PeriodicalIF":0.0,"publicationDate":"2013-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2013.2279324","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62450976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Privacy Through Obscurity 通过模糊实现隐私
IEEE Design & Test of Computers Pub Date : 2013-10-01 DOI: 10.1109/MDAT.2013.2283595
S. Davidson
{"title":"Privacy Through Obscurity","authors":"S. Davidson","doi":"10.1109/MDAT.2013.2283595","DOIUrl":"https://doi.org/10.1109/MDAT.2013.2283595","url":null,"abstract":"h I RECENTLY READ an editorial in an electronics magazine about license plate readers, devices used by police and government to scan license plates on cars, look them up in a database, and report if the car is stolen or if the owner of the car is wanted by the law. Information about the location of cars whose licenses are read is kept a long time, a potential privacy problem. Even plates of cars not involved in nefarious activities are scanned. Because license plates are displayed in public, it is perfectly legal to record them. This is not the only way in which we are being recorded. In the old days, if the police wanted to find out what happened at a particular location, they had to find witnesses. Today, police can also consult footage from the large number of surveillance cameras in the area. In England, these are owned by the government, but in the United States, there seem to be just as many owned by businesses, not to mention the prevalence of cell phone cameras. In Russia, many cars use dashboard-mounted cameras, and so the recent meteorite event was captured. Even meteorite privacy is not safe. Anyone having the slightest involvement in computer security knows that ‘‘security through obscurity’’ is one of the worst policies to follow. This policy tries to keep security holes secret, and hopes that no one finds out. This might have worked when access to computers was controlled by a small set of professionals, but today even the slightest flaw will be broadcast around the world as fast as a video of a cute kitten. Those of us well out of college grew up in a time of what we can call ‘‘privacy through obscurity.’’ Perhaps people could read your license plate, but unless your car was very suspicious and you were unlucky, it was unlikely that anyone would record it or even notice it. Unless you were famous, no one but friends would take your picture. Politicians and Hollywood stars learned to live with constant exposure and loss of privacy, but at least they were well compensated. One unexpected side effect of work by engineers and computer scientists is that we are all Hollywood stars. But we don’t make the big bucks. Technology has made it possible for our public presence to be recorded and stored. Today, at least a person has to watch the videos to see if you are in themVwork is being done on automating this also. Our privacy through obscurity is no more. Gordon Bell has a project of recording his entire life. Today, we are all Gordon Bell. I’ve often wondered when he’d have time to look at this. However, I can imagine software that could look through streams of video and other information and go right to the moments you want to reliveVor the moments some observer wants to look at more closely. We tell our kids to be careful of their on-line presences, because someone might be watching. Perhaps they are well ahead of us. Someone will always be watching, in real life as well as on-line, and our kids are just getting ready for a world of li","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"30 1","pages":"96-96"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2013.2283595","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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