Microelectronics International最新文献

{"title":"Effect of nucleation layer thickness on reducing dislocation density in AlN layer for AlGaN-based UVC LED","authors":"M. Samsudin, Y. Yusuf, N. Zainal, A. Bakar, C. Zollner, M. Iza, S. Denbaars","doi":"10.1108/MI-02-2021-0012","DOIUrl":"https://doi.org/10.1108/MI-02-2021-0012","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to investigate the influence of AlN nucleation thickness in reducing the threading dislocations density in AlN layer grown on sapphire substrate.\u0000\u0000\u0000Design/methodology/approach\u0000In this work, the effect of the nucleation thickness at 5 nm, 10 nm and 20 nm on reducing the dislocation density in the overgrown AlN layer by metal organic chemical vapor deposition was discussed. The AlN layer without the nucleation layer was also included in this study for comparison.\u0000\u0000\u0000Findings\u0000By inserting the 10 nm thick nucleation layer, the density of the dislocation in the AlN layer can be as low as 9.0 × 108 cm−2. The surface of the AlN layer with that nucleation layer was smoother than its counterparts.\u0000\u0000\u0000Originality/value\u0000This manuscript discussed the influence of nucleation thickness and its possible mechanism in reducing dislocations density in the AlN layer on sapphire. The authors believe that the finding will be of interest to the readers of this journal, in particular those who are working on the area of AlN.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42805004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The role of growth temperature on the indium incorporation process for the MOCVD growth of InGaN/GaN heterostructures","authors":"A. S. Yusof, Z. Hassan, S. O. Hamady, S. Ng, M. A. Ahmad, W. F. Lim, Muhd Azi Che Seliman, C. Chevallier, N. Fressengeas","doi":"10.1108/MI-02-2021-0018","DOIUrl":"https://doi.org/10.1108/MI-02-2021-0018","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to investigate the effect of growth temperature on the evolution of indium incorporation and the growth process of InGaN/GaN heterostructures.\u0000\u0000\u0000Design/methodology/approach\u0000To examine this effect, the InGaN/GaN heterostructures were grown using Taiyo Nippon Sanso Corporation metal-organic chemical vapor deposition (MOCVD) SR4000-HT system. The InGaN/GaN heterostructures were epitaxially grown on 3.4 µm undoped-GaN (ud-GaN) and GaN nucleation layer, respectively, over a commercial 2” c-plane flat sapphire substrate. The InGaN layers were grown at different temperature settings ranging from 860°C to 820°C in a step of 20°C. The details of structural, surface morphology and optical properties were investigated using X-ray diffraction (XRD), field emission scanning electron microscope (FE-SEM), atomic force microscopy and ultraviolet-visible (UV-Vis) spectrophotometer, respectively.\u0000\u0000\u0000Findings\u0000InGaN/GaN heterostructure with indium composition up to 10.9% has been successfully grown using the MOCVD technique without any phase separation detected within the sensitivity of the instrument. Indium compositions were estimated through simulation fitting of the XRD curve and calculation of Vegard’s law from UV-Vis measurement. The thickness of the structures was determined using the Swanepoel method and the FE-SEM cross-section image.\u0000\u0000\u0000Originality/value\u0000This paper report on the effect of MOCVD growth temperature on the growth process of InGaN/GaN heterostructure, which is of interest in solid-state lighting technology, especially in light-emitting diodes and solar cell application.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45349783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Structural and mechanical properties of a-axis AlN thin films growth using reactive RF magnetron sputtering plasma","authors":"A. S. Bakri, N. Nayan, C. Soon, M. K. Ahmad, A. Bakar, Wan Haliza Abd Majid, N. A. Raship","doi":"10.1108/MI-02-2021-0015","DOIUrl":"https://doi.org/10.1108/MI-02-2021-0015","url":null,"abstract":"\u0000Purpose\u0000This paper aims to report the influence of sputtering plasma deposition time on the structural and mechanical properties of the a-axis oriented aluminium nitride (AlN) thin films.\u0000\u0000\u0000Design/methodology/approach\u0000The AlN films were prepared using RF magnetron sputtering plasma on a silicon substrate without any external heating with various deposition times. The films were characterized using X-ray diffraction (XRD), field-emission scanning electron microscope (FESEM), atomic force microscope (AFM) and nanoindentation techniques.\u0000\u0000\u0000Findings\u0000The XRD results show that the AlN thin films are highly oriented along the (100) AlN plane at various deposition times indicating the a-axis preferred orientation. All the AlN thin films exhibit hexagonal AlN with a wurtzite structure. The hardness and Young’s modulus of AlN thin films with various deposition times were measured using a nanoindenter. The measured hardness of the AlN films on Si was in the range of 14.1 to 14.7 GPa. The surface roughness and the grain size measured using the AFM revealed that both are dependent on the deposition times.\u0000\u0000\u0000Originality/value\u0000The novelty of this work lies with a comparison of hardness and Young’s modulus result obtained at different sputtering deposition temperature. This study also provides the relation of AlN thin films’ crystallinity with the hardness of the deposited films.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48172982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm","authors":"N. Idros, A. Rosli, Z. Aziz, J. Rajendran, A. Marzuki","doi":"10.1108/MI-10-2020-0073","DOIUrl":"https://doi.org/10.1108/MI-10-2020-0073","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures.\u0000\u0000\u0000Design/methodology/approach\u0000The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V.\u0000\u0000\u0000Findings\u0000Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion.\u0000\u0000\u0000Originality/value\u0000This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45305051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adapting M2 silicon half-wafers processing on industrial-scale equipment dedicated to 4″ solar technology","authors":"M. Boumaour, S. Kermadi, S. Sali, Abdelkader El-Amrani, S. Mezghiche, L. Zougar, Sarah Boulahdjel, Y. Pellegrin","doi":"10.1108/MI-09-2020-0065","DOIUrl":"https://doi.org/10.1108/MI-09-2020-0065","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6'' half-cut cell with its many advantages appears promising insofar as it offers the possibility of further extend the use of costly, still operational process equipment, but doomed to obsolescence.\u0000\u0000\u0000Design/methodology/approach\u0000In the background of a detailed Al-BSF process, the authors show how to experimentally adapt specific accessories and arrange 6” half-wafers to enable the upgrade of a complete industrial process of silicon solar cells at a lower cost. Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput.\u0000\u0000\u0000Findings\u0000Globally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch.\u0000\u0000\u0000Originality/value\u0000In terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43032872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of different temperature distribution on multi-stack BGA package","authors":"L. H. Tung, Fei Chong Ng, A. Abas, M. Z. Abdullah, Zambri Samsudin, M. Y. Tura Ali","doi":"10.1108/MI-10-2020-0066","DOIUrl":"https://doi.org/10.1108/MI-10-2020-0066","url":null,"abstract":"\u0000Purpose\u0000This paper aims to determine the optimum set of temperatures through correlation study to attain the most effective capillary flow of underfill in a multi-stack ball grid array (BGA) chip device.\u0000\u0000\u0000Design/methodology/approach\u0000Finite volume method is implemented in the simulation. A three-layer multi-stack BGA is modeled to simulate the underfill flow. The simulated models were well validated with the previous experimental work on underfill process.\u0000\u0000\u0000Findings\u0000The completion filling time shows high regression R-squared value of up to 0.9918, which indicates a substantial acceleration on the underfill process because of incorporation of thermal delta. An introduction of 11 °C thermal delta to the multi-stacks BGA managed to reduce the filling time by up to 16.4%.\u0000\u0000\u0000Practical implications\u0000Temperature-induced capillary flow is a relatively new type of driven underfill designed specifically for package on package BGA components. Its simple implementation can further improve the productivity of existing underfill process in the industry that is desirable in reducing the process lead time.\u0000\u0000\u0000Originality/value\u0000The effect of temperature-induced capillary flow in underfill encapsulation on multi-stacks BGA by means of statistical correlation study is a relatively new topic, which has never been reported in any other research according to the authors’ knowledge.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48707685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An investigation of physical properties and photovoltaic performance of methylammonium lead-tin iodide (CH3NH3Sn1-xPbxI3) solar cells","authors":"O. Malekan, M. Adelifard, M. M. Mohagheghi","doi":"10.1108/MI-09-2020-0064","DOIUrl":"https://doi.org/10.1108/MI-09-2020-0064","url":null,"abstract":"In the past several years, CH3NH3PbI3 perovskite material has been extensively evaluated as an absorber layer of perovskite solar cells due to its excellent structural and optical properties, and greater than 22% conversion efficiency. However, improvement and future commercialization of solar cells based on CH3NH3PbI3 encountered restrictions due to toxicity and instability of the lead element. Recently, studies on properties of lead-free and mixture of lead with other cations perovskite thin films as light absorber materials have been reported. The purpose of this paper was the fabrication of CH3NH3Sn1-xPbxI3 thin films with different SnI2 concentrations in ambient condition, and study on the structural, morphological, optical, and photovoltaic performance of the studied solar cells. The X-ray diffraction studies revealed the formation of both CH3NH3PbI3 and CH3NH3SnI3 phases with increasing the Sn concentration, and improvement in crystallinity and morphology was also observed. All perovskite layers had a relatively high absorption coefficient >104 cm−1 in the visible wavelengths, and the bandgap values varied in the range from 1.46 to 1.63 eV. Perovskite solar cells based on these thin films have been fabricated, and device performance was investigated. Results showed that photo-conversion efficiency (PCE) for the pure CH3NH3PbI3sample was 1.20%. With adding SnI2, PCE was increased to 4.48%.,In this work, the author mixed tin and lead with different percentages in the perovskite thin film. Also, the preparation of these layers and also other layers to fabricate solar cells based on them were conducted in an open and non-glove box environment. Finally, the effect of [Sn/Pb] ratio in the CH3NH3Sn1-xPbxI3 layers on the structural, morphological, optical, electrical and photovoltaic performance have been investigated.,CH3NH3Sn1-xPbxI3 (x = 0.0, 0.25, 0.50, 0.75, 1.0) perovskite thin films have been grown by a spin-coating technique. It was found that as tin concentration increases, the X-ray diffraction and FESEM images studies revealed the formation of both CH3NH3PbI3 and CH3NH3SnI3 phases, and improvement in crystallinity, and morphology; all thin films had high absorption coefficient values close to 104 cm−1 in the visible region, and the direct optical bandgap in the layers decreases from 1.63 eV in pure CH3NH3SnI3 to 1.46 eV for CH3NH3Sn0.0.25Pb0.75I3 samples; all thin films had p-type conductivity, and mobility and carrier density increased; perovskite solar cells based on these thin films have been fabricated, and device performance was investigated. Results showed that photo-conversion efficiency (PCE) for the pure CH3NH3PbI3sample was 1.20%. With adding SnI2, PCE was increased to 4.48%.,The preparation method seems to be interesting as it is in an ambient environment without the protection of nitrogen or argon gas.","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42937746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced utilization of 3D digital image correlation for thermal and impact reliabilities of electronics components","authors":"J. Kwak, Soonwan Chung","doi":"10.1108/MI-08-2020-0052","DOIUrl":"https://doi.org/10.1108/MI-08-2020-0052","url":null,"abstract":"\u0000Purpose\u0000This paper aims to present an adaptation of digital image correlation (DIC) to the electronics industry for reliability assessment of electronic packages. Two case studies are presented: one for warpage measurement of a micro-electro-mechanical system (MEMS) package under different temperature conditions and the other for the measurement of transient displacements on the surface of a printed circuit board (PCB) assembly under free-fall drop conditions, which is for explaining the typical camera setup requirement and comparing among different boundary conditions by fastening methods of PCB.\u0000\u0000\u0000Design/methodology/approach\u0000DIC warpage measurements on a small device, such as a MEMS package, require a special speckle pattern. A new method for the creation of speckle patterns was developed using carbon coating and aluminum evaporative deposition. To measure the transient response on the surface of a PCB during a free-fall impact event, three-dimensional (3D) DIC was integrated with synchronized stereo-high speed cameras. This approach enables the measurement of full-field displacement on the PCB surface during a free-fall impact event, contrary to the localized information that is obtained by the conventional strain gage and accelerometer method.\u0000\u0000\u0000Findings\u0000The authors suggest the proposed patterning method to the small-sized microelectronics packages for DIC measurements. More generally, the idea is to have a thin layer of the dark or bright color of the background and then apply the white or black colored pattern, respectively, so that the surface has high contrast. Also, to achieve a proper size of speckles, this paper does not want to expose the measuring objects to high temperatures or pressures during the sample preparation stage. Of course, it seems a complicated process to use aluminum evaporator, carbon coater and electroformed mesh. However, the authors intend to share one of the solutions to achieve a proper pattern on such small-sized electronic packages.\u0000\u0000\u0000Originality/value\u00003D DIC technique can be successfully implemented for the measurement of micro-scale deformations in small packages (such as MEMS) and for the analysis of dynamic deformation of complex PCB.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43461439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Small ozone generator fabricated from low-temperature co-fired ceramics","authors":"K. Makarovič, D. Belavic, B. Malič, A. Benčan, F. Kovač, J. Holc","doi":"10.1108/MI-07-2020-0043","DOIUrl":"https://doi.org/10.1108/MI-07-2020-0043","url":null,"abstract":"The purpose of this study is the design, fabrication and evaluation of a miniature ozone generator using the principle of electric discharge are presented.,The device was fabricated using a low-temperature co-fired ceramics (LTCC) technology, by which a multilayered ceramic structure with integrated electrodes, buried channels and cavities in micro and millimeter scales was realized.,The developed ozone generator with the dimensions of 63.6 × 41.8 × 1.3 mm produces approximately 1 vol. % of ozone in oxygen flow of 15 ml/min, at an applied voltage of 7 kV.,A miniature ozone generator, manufactured in LTCC technology, produces high amount of ozone and more than it is described in the available references or in datasheets of commercial devices of similar size.","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46324945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancement of luminous flux of InGaAlP-based low-power SMD LEDs using substrates with different thermal resistances","authors":"M. E. Raypah, S. Mahmud, M. Devarajan, A. Alshammari","doi":"10.1108/mi-06-2020-0035","DOIUrl":"https://doi.org/10.1108/mi-06-2020-0035","url":null,"abstract":"\u0000Purpose\u0000Optimization of light-emitting diodes’ (LEDs’) design together with long-term reliability is directly correlated with their photometric, electric and thermal characteristics. For a given thermal layout of the LED system, the maximum luminous flux occurs at an optimal electrical input power and can be determined using a photo-electro-thermal (PET) theory. The purpose of this study is to extend the application of the luminous flux equation in PET theory for low-power (LP) LEDs.\u0000\u0000\u0000Design/methodology/approach\u0000LP surface-mounted device LEDs were mounted on substrates of different thermal resistances. Three LEDs were attached to substrates which were flame-retardant fiberglass epoxy (FR4) and two aluminum-based metal core printed circuit boards (MCPCBs) with thermal conductivities of about 1.0 W/m.K, 2.0 W/m.K and 5.0 W/m.K, respectively. The conjunction of thermal transient tester and thermal and radiometric characterization of LEDs system was used to measure the thermal and optical parameters of the LEDs at a certain range of input current and temperature.\u0000\u0000\u0000Findings\u0000The validation of the extended application of the luminous flux equation was confirmed via a good agreement between the practical and theoretical results. The outcomes show that the optimum luminous flux is 25.51, 31.91 and 37.01 lm for the LEDs on the FR4 and the two MCPCBs, respectively. Accordingly, the stipulated maximum electrical input power in the LED datasheet (0.185 W) is shifted to 0.6284, 0.6963 and 0.8838 W between the three substrates.\u0000\u0000\u0000Originality/value\u0000Using a large number of LP LEDs is preferred than high-power (HP) LEDs for the same system power to augment the heat transfer and provide a higher luminous flux. The PET theory equations have been applied to HP LEDs using heatsinks with various thermal resistances. In this work, the PET theory luminous flux equation was extended to be used for Indium Gallium Aluminum Phosphide LP LEDs attached to the substrates with dissimilar thermal resistances.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2020-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45351166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}