发布求助
文献互助 智能选刊 最新文献

Proceedings of 7th International Conference on VLSI Design最新文献

筛选
英文 中文
An optimal design for parallel test generation based on circuit partitioning 基于电路划分的并行测试生成优化设计
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282706
Dong Xiang, D. Wei
{"title":"An optimal design for parallel test generation based on circuit partitioning","authors":"Dong Xiang, D. Wei","doi":"10.1109/ICVD.1994.282706","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282706","url":null,"abstract":"A parallel testing graph (PTG) is offered to deal with the test scheduling problem; test scheduling in this paper refers to finding an optimal test generation scheme that allocates subcircuits or part of each subcircuit to the processors in a multiprocessor system. Test generation of subcircuits that can be run simultaneously should not share the same multiplexer in the process of test generation. The test scheduling problem is reduced to the vertex coloring of the PTG; and then the test scheduling problem is found to be solvable in quadratic time. Certainly, the number of sequential test generation events is equal to the vertex chromatic number of the PTG. The problem is how to minimize the vertex chromatic number of the PTG. On the basis of these results, an integer linear programming model is offered to design for maximum parallelism of the test generation problem, which minimizes the vertex chromatic number of the PTG, and thereby, maximizes the parallelism of the problem.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Layout influenced factorization of Boolean functions 布局影响布尔函数的分解
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282696
A. Jaekel, S. Bandyopadhyay, A. Sengupta
{"title":"Layout influenced factorization of Boolean functions","authors":"A. Jaekel, S. Bandyopadhyay, A. Sengupta","doi":"10.1109/ICVD.1994.282696","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282696","url":null,"abstract":"Traditional approaches to designing VLSI circuits for a given Boolean function usually treat logic minimization and layout generation as two separate subproblems which are solved independently of each other. However, actual layout considerations such as transistor placement and the routing strategy are also important factors in determining the cost of a combinational circuit. Our approach tries to factorize Boolean functions in such a way that the corresponding functional cell layout area is minimized.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115555010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic simulation using an asynchronous parallel discrete-event simulation model on a SIMD machine 在SIMD机器上使用异步并行离散事件仿真模型进行逻辑仿真
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282635
S. Seth, L. Gowen, Matt Payne, Don Sylwester
{"title":"Logic simulation using an asynchronous parallel discrete-event simulation model on a SIMD machine","authors":"S. Seth, L. Gowen, Matt Payne, Don Sylwester","doi":"10.1109/ICVD.1994.282635","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282635","url":null,"abstract":"The Chandy-Misra-Bryant (CMB) model has been applied to logic simulation of synchronous sequential circuits using a massively parallel SIMD computer, a CM-2 Connection Machine. Several methods of reducing message traffic in a logic simulation have been adapted to the SIMD architecture of the CM-2, with the result that each method of reducing message traffic actually decreases the speed of the simulation. This suggests that communication costs required to support logic simulation are small compared to the cost of deciding which messages need not be sent.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122463318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
nOHM/spl minus/a multi-process device synthesis tool for lateral DMOS structures 用于横向DMOS结构的nOHM/spl - /多工艺器件合成工具
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282712
S. Natarajan, D. Sahu, S. Dasgupta
{"title":"nOHM/spl minus/a multi-process device synthesis tool for lateral DMOS structures","authors":"S. Natarajan, D. Sahu, S. Dasgupta","doi":"10.1109/ICVD.1994.282712","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282712","url":null,"abstract":"This paper presents a synthesis tool that generates layouts of Lateral Doubly-Diffused MOS (LDMOS) structures from electrical parameters of the device or from the current and thermal requirements of the package. Optionally, it generates layouts from physical parameters like DMOS width, area and floorplan constraints. Multiple layout and metal bus styles are supported. Source and drain sense DMOSs used to sample currents of the parent devices can also be generated and automatically placed inside the DMOS. The generated layouts are correct by construction. The tool has been developed for the Intelligent Power family of integrated circuits from Texas Instruments Inc. In this paper the need, capabilities and impact of the tool are presented along with the techniques used to achieve them.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OTA based neural network architectures with on-chip tuning of synapses 基于OTA的神经网络架构与片上调谐的突触
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282659
Joydeep Ghosh, P. LaCour, S. Jackson
{"title":"OTA based neural network architectures with on-chip tuning of synapses","authors":"Joydeep Ghosh, P. LaCour, S. Jackson","doi":"10.1109/ICVD.1994.282659","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282659","url":null,"abstract":"We propose and analyze analog VLSI implementations of neural networks in which both the neural cells and the synapses are realized using Operational Transconductance Amplifiers (OTAs). These circuits have inherent advantages of immunity to noise, very high input/output impedances, differential architecture with automatic inversion, and density. An efficient on-chip technique for weight adaptation and for adjusting the gain of OTA-based neurons is proposed. Power and area requirements are obtained. We consider OTAs as a basic building block for efficiently constructing several types of artificial neural networks including Hopfield networks, Boltzmann machines and cellular networks. Circuit simulations using MTIME show that small Hopfield memories converge in about a /spl mu/sec.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128456042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Multiobjective search in VLSI design VLSI设计中的多目标搜索
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282726
P. Dasgupta, P. Mitra, P. Chakrabarti, S. Sarkar
{"title":"Multiobjective search in VLSI design","authors":"P. Dasgupta, P. Mitra, P. Chakrabarti, S. Sarkar","doi":"10.1109/ICVD.1994.282726","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282726","url":null,"abstract":"Many optimization problems in VLSI design involve multiple, conflicting and non-commensurate objectives. The multiobjective approach, which models each objective by a scalar-valued criterion and attempts to find all non-dominated solutions, is a natural and efficient alternative to the conventional practice of combining all objectives into a single optimization criterion. In this paper we illustrate the multiobjective search approach MObj By applying it on two well known problems in VLSI, namely the scheduling problem in high level synthesis and the channel routing problem in layout synthesis. The efficiency of MObj and its linear space version SMObj is demonstrated by comparing their performances with multiobjective generalizations of the single objective strategies A* and DFBB.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123477114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An efficient hybrid heuristic for the gate matrix layout problem in VLSI design VLSI设计中栅极矩阵布局问题的一种高效混合启发式算法
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282686
T. Bagchi, Sajal K. Das
{"title":"An efficient hybrid heuristic for the gate matrix layout problem in VLSI design","authors":"T. Bagchi, Sajal K. Das","doi":"10.1109/ICVD.1994.282686","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282686","url":null,"abstract":"In this paper, we consider the gate matrix layout problem in VLSI design, where the goal is to minimize the number of tracks required to layout a given circuit. An efficient hybrid heuristic algorithm is proposed to solve this combinatorial optimization problem, which is based on the combination of the probabilistic hill-climbing technique and a greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126504697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HSIM1 and HSIM2: object oriented algorithms for VHDL simulation HSIM1和HSIM2:面向对象的VHDL仿真算法
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282679
Neeta Ganguly, V. Pitchumani
{"title":"HSIM1 and HSIM2: object oriented algorithms for VHDL simulation","authors":"Neeta Ganguly, V. Pitchumani","doi":"10.1109/ICVD.1994.282679","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282679","url":null,"abstract":"In this paper we present two algorithms, HSIM1 and HSIM2, for the simulation of VHDL circuit descriptions. HSIM1 and HSIM2 are both object-oriented event-driven algorithms which maintain the hierarchical nature of the simulation network. The objects in the system are instances of classes which are classes are created by compiling VHDL code into C++. These algorithms have been implemented and tested on several examples and have been found to perform much better than the Intermetrics VHDL simulator, which is an industry standard.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128161084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A BIST PLA design for high fault coverage and testing by an interleavingly crosspoint counting 一个BIST PLA设计用于高故障覆盖率和交错交叉点计数测试
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282668
M. Mottalib, P. Dasgupta
{"title":"A BIST PLA design for high fault coverage and testing by an interleavingly crosspoint counting","authors":"M. Mottalib, P. Dasgupta","doi":"10.1109/ICVD.1994.282668","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282668","url":null,"abstract":"A built-in-self testable (BIST) programmable logic array (PLA) is designed where an interleaving counting technique of crosspoint (cp) devices on the product lines has been used. The proposed technique reduces the test application time by a substantial amount. To implement this idea, the product lines are re-arranged according to the number of cp devices. After re-arranging, if two consecutive product lines differ by more than one cp device then a single product line is added in between these two lines in contrast to multiple ones. The test pattern generator and response evaluator circuits are simple and consist of mainly shift registers and counters which reduce the delay per test as opposed to conventional parity checkers. The proposed technique has extremely high fault coverage. All the single faults and most of the multiple faults are covered. Even in the worst case, the fault coverage is close to 100%.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 600 MHz half-bit level pipelined multiplier macrocell 一个600兆赫半比特级的流水线乘法器
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282664
D. Ghosh, S. Sural, S. Nandy
{"title":"A 600 MHz half-bit level pipelined multiplier macrocell","authors":"D. Ghosh, S. Sural, S. Nandy","doi":"10.1109/ICVD.1994.282664","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282664","url":null,"abstract":"In this paper a high throughput 8/spl times/8 bit multiplier in a 0.8 /spl mu/ CMOS process is described. A novel pipelining technique in NPCPL (normal process complementary pass transistor logic) allows fine grain pipelining with minimal overhead of area and latency. This is in contrast to conventional approaches where highly pipelined designs are constrained by area and latency overhead of pipeline latches. A two-stage full adder is employed in a carry-save array architecture. The 0.95 mm/spl times/0.87 mm multiplier core supports a throughput of 600 MHz with a power dissipation of 0.9 Watt. Since such a high speed clock cannot be routed from the external world, the clock is generated on-chip. The on-chip clock generator ensures generation of non-overlapping clocks under all conditions of process parameter variations. This along with proper design of clock buffers and clock distribution network minimises clock skew to allow high speed clocking.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130462674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书