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Proceedings of 7th International Conference on VLSI Design最新文献

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SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement 遗传算法与模拟退火算法的统一及其在宏细胞定位中的应用
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282687
H. Esbensen, P. Mazumder
{"title":"SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement","authors":"H. Esbensen, P. Mazumder","doi":"10.1109/ICVD.1994.282687","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282687","url":null,"abstract":"In this paper a stochastic optimization algorithm called SAGA is presented, which is a generalization of the genetic algorithm and the simulated annealing algorithm. Depending on the settings of its control parameters, SAGA executes as a genetic algorithm, a simulated annealing algorithm, or a mixture of these. SAGA represents an application independent approach to optimization, and the resulting search process is highly adaptive. The performance of the approach on the macro-cell placement problem is examined. It is experimentally shown that a mixture of the genetic algorithm with simulated annealing yields higher layout quality than a pure genetic algorithm. Furthermore, layout qualities obtained by SAGA on MCNC benchmarks are comparable to or better than previously published results.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130232780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
High speed digital filtering on SRAM-based FPGAs 基于sram的fpga高速数字滤波
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282691
A. Giri, V. Visvanathan, S. Nandy, S. Ghoshal
{"title":"High speed digital filtering on SRAM-based FPGAs","authors":"A. Giri, V. Visvanathan, S. Nandy, S. Ghoshal","doi":"10.1109/ICVD.1994.282691","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282691","url":null,"abstract":"Field programmable gate arrays (FPGAs) represent a very promising technology that attempts to provide the benefits of custom VLSI with low turn-around time. However, the applicability of this technology for serious DSP applications, that are compute-intensive and typically demand high throughput, has not yet been fully explored. As a case study, real time digital FIR filters of both the constant and programmable coefficient types are considered. Two filters, one of each type, have been successfully implemented in SRAM-based FPGA parts. In the process of design, several generic issues surfaced: the most important among them being efficient utilisation of routing resources. As ever-improving process technology enables higher and higher speeds of operation, density seems to be the more important deciding factor for the feasibility of such applications on FPGAs.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115627181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A VLSI architecture of an inverse discrete cosine transform 一个反离散余弦变换的VLSI结构
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282662
A. Bhattacharya, S. S. Haider
{"title":"A VLSI architecture of an inverse discrete cosine transform","authors":"A. Bhattacharya, S. S. Haider","doi":"10.1109/ICVD.1994.282662","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282662","url":null,"abstract":"The inverse discrete cosine transform (IDCT) is an important function in HDTV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the sequence of input coefficients and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity which is suitable for VLSI implementation. Based on this technique, an architecture using only seven constant multipliers and only one 1 dimensional IDCT processor is presented.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116534188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Response pipelined CAM chips: the first generation and beyond 响应流水线CAM芯片:第一代及以后
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282720
K. Ghose, V. Dharmaraj
{"title":"Response pipelined CAM chips: the first generation and beyond","authors":"K. Ghose, V. Dharmaraj","doi":"10.1109/ICVD.1994.282720","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282720","url":null,"abstract":"Response-pipelined CAM (RPCAM) chips with W-bit wide words are designed to be cascadable to implement an associative array with a effective word size of K*W bits, where K is a positive integer, and allow a constant search rate of one search per cycle, irrespective of K, without the need for complex wiring or external glue logic. RPCAMs are useful as accelerators for search-intensive applications that use large key sizes. We describe the architecture of the first generation of RPCAMs and an assessment of the 2-micron prototype implementation. We also present an overview of the architecture for the second generation of RPCAMs.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast algorithm for performing vector quantization and its VLSI implementation 一种矢量量化的快速算法及其VLSI实现
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282663
Heonchul Park, V. Prasanna
{"title":"A fast algorithm for performing vector quantization and its VLSI implementation","authors":"Heonchul Park, V. Prasanna","doi":"10.1109/ICVD.1994.282663","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282663","url":null,"abstract":"In this paper, we propose a new tree search algorithm for performing vector quantization (VQ), and a processor and area efficient architecture for implementing it. The proposed algorithm consists of two phases: in the first phase, we perform a fast approximate search without using multiplication. In the second phase, we employ a known tree search algorithm on the neighborhood of the codevector found in the first phase. The size of the search space in the second phase depends on the desired image quality. For obtaining image quality comparable to the known tree (full) search based VQ, the proposed algorithm takes O(klogloglogN) (O(kloglogN)) time units, where N is the number of codevectors and k is the number of dimensions. In the proposed architecture, O(logloglogN) and O(loglogN) processing elements are used to obtain image quality which is comparable to those produced by the known tree search and full search based VQ, respectively. These implementations support real time operations.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127696846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A linear systolic array for LU decomposition 用于LU分解的线性收缩阵列
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282718
E. Casseau, D. Degrugillier
{"title":"A linear systolic array for LU decomposition","authors":"E. Casseau, D. Degrugillier","doi":"10.1109/ICVD.1994.282718","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282718","url":null,"abstract":"Systolic machines or arrays are devices attached to a conventional computer to perform special-purpose functions with extremely high speed. This paper presents a systolic array for decomposing a matrix into its lower and upper triangular factors (LU decomposition). The chip we present is based on a linear systolic array and has interesting features such as a reduced number of cells and few I/Os. It is shown how the computations should be performed on band matrices which occur in several numerical problems, particularly in finite element analysis.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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