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Proceedings of 7th International Conference on VLSI Design最新文献

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Behavioral design and prototyping of a fail-safe system 故障安全系统的行为设计和原型
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282676
Y. Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan
{"title":"Behavioral design and prototyping of a fail-safe system","authors":"Y. Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan","doi":"10.1109/ICVD.1994.282676","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282676","url":null,"abstract":"This paper presents a methodology for designing and prototyping a fail-safe system at behavioral level. The theoretical framework for fail-safe circuits in the literature is difficult to apply in practice because of the complexity of practical systems. In this paper, a fail-safe system is defined at the behavioral level. The fail-safe rules in the system specification allow fault-tree analysis to verify the fail-safeness. To illustrate the methodology, a microprocessor-based fail-safe system for interlocking on railways is presented.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131014326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On testability of differential split-level CMOS circuits 差分分电平CMOS电路的可测试性研究
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282683
S. M. Aziz, W. Waller
{"title":"On testability of differential split-level CMOS circuits","authors":"S. M. Aziz, W. Waller","doi":"10.1109/ICVD.1994.282683","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282683","url":null,"abstract":"Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analyzed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of these faults can be detected by current monitoring.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Rapid technology projection for high-level synthesis 高水平合成的快速技术投影
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282675
P. Jha, N. Dutt
{"title":"Rapid technology projection for high-level synthesis","authors":"P. Jha, N. Dutt","doi":"10.1109/ICVD.1994.282675","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282675","url":null,"abstract":"High-level synthesis (HLS) tools often use parameterized RT component generators during component selection and allocation. Rapid and accurate technology-specific estimates are therefore crucial for performing effective design space exploration. We describe a fast (on-line) method for estimating the area and delay of regular-structured generic RT components tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample technology data points from selected component implementations. We tested these models against real data points on combinational and sequential components and observed an average error of within 10%. The estimators are integrated with a HLS system to provide on-line technology projection of RT components.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114851379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bitwise encoding of finite state machines 有限状态机的位编码
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282723
J. Monteiro, J. Kukula, S. Devadas, H. Neto
{"title":"Bitwise encoding of finite state machines","authors":"J. Monteiro, J. Kukula, S. Devadas, H. Neto","doi":"10.1109/ICVD.1994.282723","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282723","url":null,"abstract":"We propose an innovative method of encoding the states of finite state machines. Our approach consists of iteratively defining the code word, one bit at a time. In each iteration the input state machine is decomposed into two submachines, with the first submachine having only two states. One bit is therefore sufficient to encode this submachine and it can be assigned arbitrarily as the particular value it assumes for each state is of minimal influence in terms of the machine implementation. The process is repeated again having as input the second submachine, until all the bits are encoded. We provide experimental results which indicate that our method of iteratively defining one bit at a time can generally achieve superior results to existing sequential state assignment methods which try to solve large problems heuristically.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123569993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High performance over-the-cell routing 高性能的蜂窝间路由
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282672
Jim E. Crenshaw, S. Tragoudas, N. Sherwani
{"title":"High performance over-the-cell routing","authors":"Jim E. Crenshaw, S. Tragoudas, N. Sherwani","doi":"10.1109/ICVD.1994.282672","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282672","url":null,"abstract":"Recently, several algorithms have been presented which use over-the-cell routing to minimize channel height in standard cell designs. A major shortcoming of the existing routers is the increase in the maximum wire length which may violate the timing constraints. In this paper, we consider the center terminal model, and the terminal assignment phase for over-the-cell routing so that the timing overhead of the routing meets a certain bound. We guarantee efficient terminal assignment by minimizing the maximum net span, a lower bound for the timing overhead, formally defined as the maximum Manhattan distance, among all nets, between the source and furthest destination on the net. We present an O(t/sup 2spl middot/logt) optimal dynamic programming algorithm for the maximum net span, and an efficient heuristic that couples net span and density minimization so that we obtain high performance routing with small channel width. Experimental results support the theoretical foundations of our approach.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126136481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power constraint scheduling of tests 测试的功率约束调度
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282700
Richard M. Chou, K. Saluja, V. Agrawal
{"title":"Power constraint scheduling of tests","authors":"Richard M. Chou, K. Saluja, V. Agrawal","doi":"10.1109/ICVD.1994.282700","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282700","url":null,"abstract":"This paper presents motivation for considering the power constraint in testing and gives a model-based formulation of the new test scheduling problem. Optimum test scheduling algorithms are presented for both equal and unequal test length cases under the power constraint. The algorithms consist of three basic steps. First, we find a complete set of time compatible tests with power dissipation information associated with each test. Second, from these tests, we extract the lists of power compatible tests. And finally, we use a minimum cover table approach to find the optimal scheduling of the tests.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
I/sub DDQ/ measurement based diagnosis of bridging faults in full scan circuits 基于I/sub DDQ/测量的全扫描电路桥接故障诊断
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282680
S. Chakravarty, S. Suresh
{"title":"I/sub DDQ/ measurement based diagnosis of bridging faults in full scan circuits","authors":"S. Chakravarty, S. Suresh","doi":"10.1109/ICVD.1994.282680","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282680","url":null,"abstract":"An algorithm for diagnosing two node bridging faults in static CMOS combinational circuits (full scan circuits) is presented. This algorithm uses results from I/sub DDQ/ testing. The bridging faults considered can be between nodes that are outputs of a gate or internal nodes of gates. Experiments on ISCAS89 circuits show that: I/sub DDQ/ measurement based diagnosis, using a small number of random vectors, is very effective; and it is computationally feasible to diagnose, using I/sub DDQ/ measurement, the large number of all bridging faults.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128669486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
On probabilistic testing of large-scale sequential circuits using circuit decomposition 基于电路分解的大规模顺序电路的概率测试
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282709
Sunil R. Das, W. Jone, A. Nayak, I. Choi
{"title":"On probabilistic testing of large-scale sequential circuits using circuit decomposition","authors":"Sunil R. Das, W. Jone, A. Nayak, I. Choi","doi":"10.1109/ICVD.1994.282709","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282709","url":null,"abstract":"In this paper the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large sequential circuit, it is partitioned into several smaller partitions using either series or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. A random testing strategy that uses a three-state Markov model is used for detecting permanent stuck faults. Experimentation on various sequential circuits has shown that a significant saving in testing or test generation time can be achieved if we can partition the circuit and then test each of its components as opposed to testing the circuit in its original form.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123718819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architecture for VLSI design of CA based byte error correcting code decoders 基于CA的字节纠错码译码器的VLSI结构设计
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282703
D. R. Chowdhury, P. P. Chaudhuri
{"title":"Architecture for VLSI design of CA based byte error correcting code decoders","authors":"D. R. Chowdhury, P. P. Chaudhuri","doi":"10.1109/ICVD.1994.282703","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282703","url":null,"abstract":"This paper reports a novel architecture for byte error correcting code decoders using Cellular Automata (CA). The chip architecture of the basic building blocks for double byte error locating/correcting code (DbEL/DbEC) is presented. Extension of the architecture to detect arbitrary number of byte errors has also been included. The proposed decoder provides a simple, modular, cascadable and cost effective design that is ideally suited for VLSI implementation.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132852535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Parallel model evaluation for circuit simulation on the PACE multiprocessor PACE多处理机电路仿真的并行模型评价
Proceedings of 7th International Conference on VLSI Design Pub Date : 1994-01-05 DOI: 10.1109/ICVD.1994.282653
P. Agrawal, Sanjay Goil, Sally Liu, J. Trotter
{"title":"Parallel model evaluation for circuit simulation on the PACE multiprocessor","authors":"P. Agrawal, Sanjay Goil, Sally Liu, J. Trotter","doi":"10.1109/ICVD.1994.282653","DOIUrl":"https://doi.org/10.1109/ICVD.1994.282653","url":null,"abstract":"Device model evaluation, an essential part of a circuit simulator, is a compute-intensive task. A multiprocessor-based circuit simulator that ignores the parallelization of model equation formulation (LOAD), and just parallelizes the solution (SOLVE) of the equations will seriously degrade the simulation performance. This paper describes methods of parallelizing the LOAD part of a circuit simulator on PACE (Parallel Architecture for Circuit Evaluation) a distributed memory multiprocessor designed at AT&T Bell Laboratories. This is integrated with the parallel SOLVE algorithms given in our earlier work. Load balancing and minimization of interprocessor communication are used as the primary objectives of the parallel LOAD heuristics studied. Performance results, using the prototype PACE system, on benchmark circuits show the feasibility of our approach.<<ETX>>","PeriodicalId":448373,"journal":{"name":"Proceedings of 7th International Conference on VLSI Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123196192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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