An efficient hybrid heuristic for the gate matrix layout problem in VLSI design

Abstract

In this paper, we consider the gate matrix layout problem in VLSI design, where the goal is to minimize the number of tracks required to layout a given circuit. An efficient hybrid heuristic algorithm is proposed to solve this combinatorial optimization problem, which is based on the combination of the probabilistic hill-climbing technique and a greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution.<>