{"title":"An Efficient ASIC Design of Variable-Length Discrete Cosine Transform for HEVC","authors":"C. V. Niras, Joshua Haddrill, Yinan Kong","doi":"10.1109/EMS.2016.047","DOIUrl":"https://doi.org/10.1109/EMS.2016.047","url":null,"abstract":"The latest video coding standard introduced by the joint collaborative team on video coding (JCT-VC) is known as high-efficiency video coding (HEVC) or H.265. HEVC/H.265 is mainly targeted for high-definition videos, and offer more compression than its predecessor. The discrete cosine transform (DCT) is widely used for image and video compression including HEVC. This paper proposes a variablelength DCT architecture for encoding video according to the HEVC/H.265 specifications. The architecture is optimized for most likely block sizes in ultra-high definition (UHD) video, and eliminates unnecessary complexities found in many architectures proposed. The synthesized results with Synopsys design tools show that the proposed method can encode 8K UHD videos @ 60 fps in real-time and accomplishes more than 60% in hardware savings.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"85 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Write Latency Reduction Techniques of State-of-the-Art Phase Change Memory","authors":"Vishal Deep, Tarek A. Elarabi","doi":"10.1109/EMS.2016.044","DOIUrl":"https://doi.org/10.1109/EMS.2016.044","url":null,"abstract":"Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Special Circuits Using State-of-the-Art Reversible Gates","authors":"Omkar Murkumbi, Tarek A. Elarabi","doi":"10.1109/EMS.2016.045","DOIUrl":"https://doi.org/10.1109/EMS.2016.045","url":null,"abstract":"The rapid advancements in VLSI industry continue to establish a smaller feature size, causing the integration of more millions of transistors on a single piece of silicon according to Moore’s law. Hence, an increase in the number of transistors induces power dissipation. Modern studies explain that power dissipation can be reduced by reversible gate technique. A central issue is the lack of use of reversible logic gates over conventional logic gates, which have enormous advantages in low-power application like portable devices, cryptography, quantum computing and nanotechnology. Different reversible gates are introduced in this research paper. Basic arithmetic and logical operations are realized from primitive level. The realized operations are used as basic blocks to design complex special adders. All introduced modules are designed using Verilog on Xilinx ISE V13.2 and ISim simulator.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124924293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cyberbullying Detection: A Survey on Multilingual Techniques","authors":"Batoul Haidar, M. Chamoun, Fadi Yamout","doi":"10.1109/EMS.2016.037","DOIUrl":"https://doi.org/10.1109/EMS.2016.037","url":null,"abstract":"Cyberbullying is the new form of bullying; executed by electronic media and Internet. Cyberbullying is affecting a lot of children around the world including Arab countries. Awareness for cyberbullying is arising and research is taking place in the fields of cyberbullying detection and mitigation and not just the psychological effects of cyberbullying on the victim. Researches on cyberbullying detection have been done in many languages but none has been done on Arabic language cyberbullying detection until the time of writing this paper. Many techniques are utilized in the area of cyberbullying detection, mainly Machine Learning (ML) and Natural Language Processing (NLP). This paper presents a brief background on cyberbullying and all technologies incorporated under this field; in addition to an extensive survey regarding the techniques and advancements in multilingual cyberbullying detection; and finally proposes a plan of a solution for the problem of Arabic cyberbullying.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"160 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128741483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis","authors":"Liang Ma, F. Muslim, L. Lavagno","doi":"10.1109/EMS.2016.036","DOIUrl":"https://doi.org/10.1109/EMS.2016.036","url":null,"abstract":"This article compares the performance and energy consumption of GPUs and FPGAs via implementing financial market models. The case studies used in this comparison are the Black-Scholes model and the Heston model for option pricing problems, which are analyzed numerically by Monte Carlo method. The algorithms are computationally intensive but not memory-intensive and thus well suited for FPGA implementation. High-level synthesis was performed starting from parallel models written in OpenCL and then various micro-architectures were explored and optimized on FPGAs. The final implementations of both models to several options on FPGAs achieved the best parallel acceleration systems, in terms of both performance-per-operation and energy-per-operation, compared not only to the kernels on advanced GPUs but also to the RTL implementations found in the literatures.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126974740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recognizing Emotional State Changes Using Speech Processing","authors":"Reza Ashrafidoost, S. Setayeshi, A. Sharifi","doi":"10.1109/EMS.2016.017","DOIUrl":"https://doi.org/10.1109/EMS.2016.017","url":null,"abstract":"Research on understanding human emotions in speech, seeks to find out utterance mood by analyzing cognitive attributes extracted from acoustical speech signal. Speech contains rich patterns which can be altered by mood of a speaker. This paper explores speech from database and long-term speech recordings to analyze of mood changing in individual speaker during long-term speech. We introduce a learning method based on statistical model to classify emotional states and moods of utterance, and also track its changes. With this object, the perceptual backgrounds of the individual speaker are analyzed, and then classified during the speech to extract patterns, which is embedded in speech signal. The proposed method, classifies emotions of the utterance in seven standard classes including, happiness, anger, boredom, fear, disgust, neutral and sadness. To this end, we call the standard speech corpus database, the EmoDB for the training phase of this approach. Thus, when pre-processing tasks done, the speech patterns and meaningful attributes have extracted by the MFCC method and selected by SFS method, and then we apply a statistical classification approach, LGMM, to categorize obtained features, and finally illustrate changes trend of the emotional states.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114595061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Continuous Fibonacci Model for Robotic Octopus Arm","authors":"A. C. Lai, P. Loreti, P. Vellucci","doi":"10.1109/EMS.2016.027","DOIUrl":"https://doi.org/10.1109/EMS.2016.027","url":null,"abstract":"We introduce a control model for an octopus robot tentacle. The model extends to a continuous setting a class of hyper-redundant planar manipulators characterized by a self-similar structure. The proposed model encompasses manipulators with a links scaling according to Fibonacci sequence. We characterize the class of continuous functions whose graph can be reparametrized as a configuration of the system and we provide an explicit control law. In particular, we give the conditions to prescribe an admissible path for the configurations of the manipulator. The result is an attempt to determine an entire class of admissible paths for the arm deformations.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129372158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Data Gathering Method Considering Volume of Transmission Range for Fish Farm Monitoring","authors":"Koichi Ishida, Y. Taniguchi, N. Iguchi","doi":"10.1109/EMS.2016.039","DOIUrl":"https://doi.org/10.1109/EMS.2016.039","url":null,"abstract":"One of the promising sensor network application is for the primary industry and we have proposed a fish farm monitoring system. In our system, sensor data monitored at a fish-mounted sensor node is transmitted to a sink node by using acoustic communication. Since we assume that a sensor node is attached at an abdominal cavity region of fish, the transmission range of acoustic wave is not omni-directional due to obstruction of fish body. In addition, energy efficient control is highly important in our system since it is difficult to replace battery of sensor node. In this paper, we propose a data gathering method taking into account energy efficiency and directional transmission range. In our method, we use the volume of transmission range to determine the timing of packet transmission. Our method does not require control packets for determining its transmission timing. Through simulation evaluations, we show that the data gathering performance of our proposed method is higher than that of comparative methods.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134493045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of Index Structures on Temporal Database Performance","authors":"Michal Kvet, K. Matiaško","doi":"10.1109/EMS.2016.012","DOIUrl":"https://doi.org/10.1109/EMS.2016.012","url":null,"abstract":"Data are inevitable part of human life. In the past, only small data portions were processed, however, nowadays, data significance and relevance is high, it is necessary to manage huge data amount, data requirements are still rising. Adding temporal data definition extends actual conventional paradigm of processing and brings real problems based on performance degradation. In this paper, we propose column level temporal architecture, which is useful for data with various frequency and time of the attribute changes. It requires sophisticated access methods for data retrieval, therefore index structures are proposed. Adding unique and reverse flag, performance results manifested by processing time can be compared. In the experiment section, impact of temporal indexing for data manipulation statement type is described, compared and evaluated.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121752412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Disaster Recovery Datacenter’s Architecture on Network Replication Solution","authors":"Hadeel A. Al-Essa, Abdulrahman A. Abdulbaki","doi":"10.1109/EMS.2016.038","DOIUrl":"https://doi.org/10.1109/EMS.2016.038","url":null,"abstract":"As the importance of network connectivity for organizations’ operations in connecting their services and business units’ increases, the need for backup sites with robust network infrastructure is crucial to achieve their business goals. To reduce cost and ease manageability and control, most organizations build one backup site. However, some organizations tend to establish multiple backup sites that host computing resources to mitigate outages that might impact their business functions and critical services. The goal of replicating network infrastructure of the backup site is to provide high availability and to ensure that critical services continue running during any event or interruption. This paper describes our experience in designing, implementing and validating network infrastructure redundancy for a disaster recovery site. In addition, it shows how the disaster recovery solution for a network infrastructure was implemented to meet the recovery objectives based on well-defined requirements and guided principles. The result proves reliability and robustness of the implemented network replication solution.","PeriodicalId":446936,"journal":{"name":"2016 European Modelling Symposium (EMS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130741173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}