2013 8th IEEE Design and Test Symposium最新文献_第7页

Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank 二维不可分滤波器组硬件实现的收缩结构

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727130

B. K. Mohanty, S. Al-Maadeed, A. Amira

{"title":"Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank","authors":"B. K. Mohanty, S. Al-Maadeed, A. Amira","doi":"10.1109/IDT.2013.6727130","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727130","url":null,"abstract":"In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non-separable filter bank. Poly-phase decomposition scheme offers multiplexing of filter bank computations or/and reduce the data clocking without affecting the overall throughput rate. Both these features can be used conveniently depending on resources availability or processor-technology. Time-multiplexing could be the choice for resource-constrained applications. Slower clocking rate could be chosen if processor-technology is the constraint. In that case, the design could be realized with cheaper and slower processor-technology. Time-multiplexed design needs proper data scheduling to perform filter bank computation interleavingly without data overlapping. Keeping this in mind, we have derived a systolic architecture for hardware realization of time-multiplexed filter bank where we have used novel data buffering scheme for the filter coefficients of the filter bank. Comparison result show that, the proposed structure involves almost J times less hardware resource than the non poly-phase filter bank structure and it provides the same throughput rate as the other, where J is the filter bank size. The hardware saving is significant for large size filter banks like Gabor. The proposed structure could be a good candidate for efficient hardware implementation of non-separable filter bank used in various image processing applications such as biometrics systems.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114689648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design space exploration and synthesis for digital signal processing algorithms from Simulink models 设计空间探索和综合数字信号处理算法从Simulink模型

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727109

S. Butt, L. Lavagno

引用次数: 7

Enabling difference-based dynamic partial self reconfiguration for large differences 为较大差异启用基于差异的动态部分自重构

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727108

Sezer Gören, Ozgur Ozkurt, Yusuf Turk, Abdullah Yildiz, H. F. Ugurdag

引用次数: 2

Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms 在多核平台中减少随机掺杂对核速度和功率可变性的影响

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727103

S. Majzoub, Z. Al-Ars, S. Hamdioui

引用次数: 2

Accurate and efficient identification of worst-case execution time for multicore processors: A survey 多核处理器最坏情况执行时间的准确和有效识别:综述

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727080

Hamid Mushtaq, Z. Al-Ars, K. Bertels

引用次数: 9

Design tradeoffs for voltage controlled crystal oscillators with built-in calibration mechanisms 具有内置校准机构的电压控制晶体振荡器的设计权衡

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727100

Jose Pedro Cardoso, J. M. D. Silva

引用次数: 0

Verifying generic IEC 61508 CPU self-tests with fault injection 验证通用IEC 61508 CPU自检与故障注入

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727145

C. Preschern, N. Kajtazovic, Andrea Höller, C. Steger, Christian Kreiner

引用次数: 2

Silicon CMOS interdigitated-MSM photodetector and self-mixer for low-cost crash-avoidance Ladar system 用于低成本防撞雷达系统的硅CMOS数字化- msm光电探测器和自混频器

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727126

E. Awad, Theodora Rezk, A. Abou-Auf

引用次数: 0

A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors 流水线微处理器中寄存器转发和流水线联锁单元的功能测试算法

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727120

P. Bernardi, D. Boyang, Lyl M. Ciganda Brasca, E. Sánchez, M. Reorda, M. Grosso, O. Ballan

{"title":"A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors","authors":"P. Bernardi, D. Boyang, Lyl M. Ciganda Brasca, E. Sánchez, M. Reorda, M. Grosso, O. Ballan","doi":"10.1109/IDT.2013.6727120","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727120","url":null,"abstract":"When the result of a previous instruction is needed in the pipeline before it is available, a “data hazard” occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RF&PI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RF&PI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power ArchitectureTM.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126530355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions 完整顺序行为的功能验证:对系统级和RTL描述之间差异的正式处理

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727074

Carlos Ivan Castro Marquez, M. Strum, J. Wang

引用次数: 0