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2007 18th European Conference on Circuit Theory and Design最新文献

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Nonlinearities: Your worst enemies…? … Your best friends! 非线性:你最大的敌人……?你最好的朋友!
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529701
M. Ogorzałek
{"title":"Nonlinearities: Your worst enemies…? … Your best friends!","authors":"M. Ogorzałek","doi":"10.1109/ECCTD.2007.4529701","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529701","url":null,"abstract":"This paper explores the problem of nonlinearities encountered in electronic circuits and systems. Nowadays commonly used by engineers are models and methods belonging to linear toolkit despite the fact that all real-world circuit elements are inherently nonlinear. We discuss the problems associated with nonlinear approach and consequences for circuit analysis and design. We stress also the fact that although in many applications the linear operation principle is of paramount importance and we make every effort to design the circuitry to operate as closely as possible to linear, there exist a vast area of applications where the nonlinearities make the circuit operation possible!","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytical calculation of BER in communication systems using a piecewise linear chaotic map 用分段线性混沌映射分析计算通信系统的误码率
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529690
Georges Kaddoum, D. Roviras, Pascal Chargé, D. Fournier-Prunaret
{"title":"Analytical calculation of BER in communication systems using a piecewise linear chaotic map","authors":"Georges Kaddoum, D. Roviras, Pascal Chargé, D. Fournier-Prunaret","doi":"10.1109/ECCTD.2007.4529690","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529690","url":null,"abstract":"The coherent reception of direct sequence-code division multiple access (DS-CDMA) is considered, when chaotic sequences are used instead of conventional pseudo-noise (PN) spreading code. A piecewise linear map (PWL) is used as chaotic spreading sequence (CSS). Additive white Gaussian noise channel (AWGN) is assumed. An analytical expression of the bit error rate in the single user case is presented.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126423778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design of fixed-width multipliers with minimum mean square error 均方误差最小的定宽乘法器设计
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529633
N. Petra, D. Caro, A. Strollo
{"title":"Design of fixed-width multipliers with minimum mean square error","authors":"N. Petra, D. Caro, A. Strollo","doi":"10.1109/ECCTD.2007.4529633","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529633","url":null,"abstract":"The paper introduces a new technique to design signed and unsigned n x n bit fixed-width multipliers with minimum mean square error. In previous papers the error minimization of fixed-width multipliers was achieved through exhaustive searches, and is practically computable only for small n values. This is the first paper in which the error compensation function of the multiplier is computed analytically, giving a result which is optimal for any value of n. The proposed approach results in improved accuracy with respect to previously proposed techniques. The paper also compares the experimental performances, in a 0.18 mum CMOS technology, of a 16 bit full-width multiplier and of a fixed-width multiplier designed with our approach. A 50% decrease of the power dissipation joined with a 13% increase of the maximum operating frequency has been measured.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130436813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A novel dual-loop multi-phase frequency synthesizer 一种新型双环多相频率合成器
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529659
Zhipeng Ye, Wenbin Chen, M. Kennedy
{"title":"A novel dual-loop multi-phase frequency synthesizer","authors":"Zhipeng Ye, Wenbin Chen, M. Kennedy","doi":"10.1109/ECCTD.2007.4529659","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529659","url":null,"abstract":"This work describes a novel dual-loop frequency synthesizer for applications in wireless communications. The synthesizer comprises a dual-loop architecture with a multi-phase voltage controlled oscillator (VCO) in one of the loops. The advantage of this architecture is the improvement of the transient response and channel spacing compared with conventional dual-loop frequency synthesizers. The proposed architecture has been implemented on a Xilinx Virtex-5 PFGA board. Measurement results confirm that the new dual-loop multi-phase frequency synthesizer achieves comparable phase noise performance but superior frequency resolution compared with the conventional dual-loop frequency synthesizer. In addition, both the in-band and out-of-band noise of the proposed architecture are improved compared with a delta-sigma modulated fractional-N frequency synthesizer.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent advances in the design of implantable stimulator output stages 植入式刺激器输出级设计的最新进展
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529572
Xiao Liu, A. Demosthenous, M. Rahal, N. Donaldson
{"title":"Recent advances in the design of implantable stimulator output stages","authors":"Xiao Liu, A. Demosthenous, M. Rahal, N. Donaldson","doi":"10.1109/ECCTD.2007.4529572","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529572","url":null,"abstract":"As the most important part of an implanted stimulation device, the stimulator output stage is in direct contact with the biological tissue, and is responsible for triggering the action potential in the stimulated nerves. The design of the stimulator output stage is governed by both biomedical and IC design constraints. In this paper, we present an overview of some recent advances in the design of implantable stimulator output stages for functional electrical stimulation applications. We also discuss a stimulator output stage structure which is suitable for large reduction of the physical size of the entire stimulator circuit.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122191717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On chip implementation of a pixel-parallel approach for retinal vessel tree extraction 一种像素并行的视网膜血管树提取方法的芯片实现
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529645
C. Alonso-Montes, P. Dudek, D. L. Vilariño, M. G. Penedo
{"title":"On chip implementation of a pixel-parallel approach for retinal vessel tree extraction","authors":"C. Alonso-Montes, P. Dudek, D. L. Vilariño, M. G. Penedo","doi":"10.1109/ECCTD.2007.4529645","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529645","url":null,"abstract":"Retinal vessel tree extraction from angiography images plays an important role not only in the medical domain, but also in biometric identification applications. From the image processing point of view, many algorithms and strategies have been developed to deal with this topic. Although reliable results have been obtained, the main disadvantage in most of these proposals is still the high computation effort required. In this paper, a methodology to extract the retinal vessel tree has been developed, specially defined in terms of fine grain SIMD processing with the purpose of improving the computation time. The proposal has been implemented on a cellular processor array VLSI chip. The execution times for the main modules of the proposed algorithm have been included to show its capability.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Arithmetic and architectural design to reduce leakage in nano-scale digital circuits 纳米数字电路中减少漏电的算法和结构设计
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529610
P. Nilsson
{"title":"Arithmetic and architectural design to reduce leakage in nano-scale digital circuits","authors":"P. Nilsson","doi":"10.1109/ECCTD.2007.4529610","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529610","url":null,"abstract":"Most of the power consumption, in standard CMOS, has in the past been related to the dynamic activities. However, in nano-meter scale technologies the static power, i.e. leakage, is an important contribution to the total power consumption. This paper discusses static and dynamic power reduction methodologies on architectural and arithmetical level. Techniques to reduce the static power consumption in digital applications for nano-scale CMOS technologies are addressed. A 79% arithmetic reduction of the static power consumption is indicated, by using serial arithmetic instead of bit-parallel. Digit-serial arithmetic shows power reductions between 32 and 67%, depending on the digit size and technology.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130894222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reduction of simultaneous switching noise in analog signal band 降低模拟信号频带的同时开关噪声
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529558
E. Backenius, M. Vesterbacka, V. B. Settu
{"title":"Reduction of simultaneous switching noise in analog signal band","authors":"E. Backenius, M. Vesterbacka, V. B. Settu","doi":"10.1109/ECCTD.2007.4529558","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529558","url":null,"abstract":"In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133696782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
EDA for RF and analog front-ends in the 4G era: Challenges and solutions 4G时代射频和模拟前端EDA:挑战与解决方案
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529527
D. Gonzalez, A. Rusu, M. Ismail
{"title":"EDA for RF and analog front-ends in the 4G era: Challenges and solutions","authors":"D. Gonzalez, A. Rusu, M. Ismail","doi":"10.1109/ECCTD.2007.4529527","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529527","url":null,"abstract":"Convergence into 4G wireless communication systems pushes the design of radio receivers beyond limits unconceivable only few years ago. The complexity of RF systems has increased enormously as new communication standards have appeared in the wireless scenario. The convergence trends, enabled by the advances in fabrication technology, have driven the software defined radio (SDR) more and more into the RF and analog front-end. There is a clear need for design automation and advanced simulation techniques at the different levels that go from the system idea to chip fabrication. Reducing the number of design iterations between these levels is key in meeting the increasingly tight time-to-market constraints. As of today, there is not a single tool that covers the complete design flow. Instead, there is an intricate puzzle of design and simulation tools that focus on the various steps that go from system to silicon. The amount of RF and analog EDA tools available is certainly scarce in comparison with their digital counterparts. Most of the design work still depends on the radio engineer, making the process less than optimal. This paper describes some of the challenges faced by today's radio designers and discusses some of the solutions provided by the EDA community.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129574743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the convergence to regime of ADC-based true random number generators 基于adc的真随机数生成器的收敛性
2007 18th European Conference on Circuit Theory and Design Pub Date : 2007-08-01 DOI: 10.1109/ECCTD.2007.4529676
R. Rovatti, S. Callegari, G. Setti
{"title":"On the convergence to regime of ADC-based true random number generators","authors":"R. Rovatti, S. Callegari, G. Setti","doi":"10.1109/ECCTD.2007.4529676","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529676","url":null,"abstract":"Reconfigurable circuits alternatively acting as random number generators (RNGs) or analog to digital converters (ADCs) represent a promising approach to true random bit generation since they can provide high quality random values almost for free whenever a system already embeds an ADC. In their usage, one needs to consider that entering the RNG-mode requires some minor interruption of operation, since the internal chaos-based random source gets initialised at the last ADC input. Hence, the first generated values maintain some dependence on a potentially known value and a few dead beats are needed by the chaotic system to reach a regime where this correlation vanishes. This delay has so far been quantified only empirically. Here, a formal bound is provided, with relation to the required performance level and the system noise floor.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132802766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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