Design of fixed-width multipliers with minimum mean square error

Abstract

The paper introduces a new technique to design signed and unsigned n x n bit fixed-width multipliers with minimum mean square error. In previous papers the error minimization of fixed-width multipliers was achieved through exhaustive searches, and is practically computable only for small n values. This is the first paper in which the error compensation function of the multiplier is computed analytically, giving a result which is optimal for any value of n. The proposed approach results in improved accuracy with respect to previously proposed techniques. The paper also compares the experimental performances, in a 0.18 mum CMOS technology, of a 16 bit full-width multiplier and of a fixed-width multiplier designed with our approach. A 50% decrease of the power dissipation joined with a 13% increase of the maximum operating frequency has been measured.