基于adc的真随机数生成器的收敛性

R. Rovatti, S. Callegari, G. Setti
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引用次数: 2

摘要

可重构电路作为随机数发生器(rng)或模数转换器(ADC)代表了一种很有前途的真正随机位生成方法,因为它们可以在系统已经嵌入ADC时几乎免费提供高质量的随机值。在它们的使用中,需要考虑进入rng模式需要一些小的操作中断,因为内部基于混沌的随机源在最后一个ADC输入时被初始化。因此,第一个生成的值对一个潜在的已知值保持一定的依赖性,混沌系统需要一些死拍才能达到这种相关性消失的状态。到目前为止,这种延迟只是经验上的量化。这里,提供了与所需性能水平和系统本底噪声有关的正式界限。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On the convergence to regime of ADC-based true random number generators
Reconfigurable circuits alternatively acting as random number generators (RNGs) or analog to digital converters (ADCs) represent a promising approach to true random bit generation since they can provide high quality random values almost for free whenever a system already embeds an ADC. In their usage, one needs to consider that entering the RNG-mode requires some minor interruption of operation, since the internal chaos-based random source gets initialised at the last ADC input. Hence, the first generated values maintain some dependence on a potentially known value and a few dead beats are needed by the chaotic system to reach a regime where this correlation vanishes. This delay has so far been quantified only empirically. Here, a formal bound is provided, with relation to the required performance level and the system noise floor.
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