{"title":"Parameter Identification of Nonlinear Systems Using a Particle Swarm Optimization Approach","authors":"W. Chang, Jun-Ping Cheng, Ming-Chieh Hsu, L. Tsai","doi":"10.1109/ICNC.2012.24","DOIUrl":"https://doi.org/10.1109/ICNC.2012.24","url":null,"abstract":"This paper applies a particle swarm optimization (PSO) approach to the parameter identification for a class of nonlinear systems. In the PSO optimization process, the unknown system parameters are arranged in the form of a parameter vector (i.e. a particle), and the PSO algorithm employs the velocity updating and position updating formulas to an initial population, which is constituted by a great number of particles, such that the excellent particle is generated. The proposed algorithm manipulates the parameter vectors directly as real numbers rather than binary strings. Therefore, to implement the PSO algorithm in computer codes becomes fairly straightforward. In this study, the PSO algorithm is applied to estimate the parameters of the Genesio-Tesi nonlinear chaotic systems. The estimation performance of the PSO algorithm is verified by examining different sets of random initial populations under the presence of measurement noises. The simulation results reveal that the PSO algorithm provides a simple and effective means of solving parameter estimation problem of nonlinear systems.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130967711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tomoyuki Nakabayashi, Takahiro Sasaki, K. Ohno, T. Kondo
{"title":"Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture","authors":"Tomoyuki Nakabayashi, Takahiro Sasaki, K. Ohno, T. Kondo","doi":"10.1109/ICNC.2012.54","DOIUrl":"https://doi.org/10.1109/ICNC.2012.54","url":null,"abstract":"Increase of energy consumption caused by processor enhancement has recently become a serious problem. Dynamic voltage and frequency scaling (DVFS) which dynamically lowers the supply voltage and clock frequency is widely used to reduce energy consumption. However, it is difficult to deliver fine-grain energy optimization by using DVFS because a voltage regulator takes a long time for scaling the voltage. To reduce energy consumption at fine-grain interval, we propose a variable stages pipeline (VSP) processor. VSP reduces energy consumption by dynamically varying the pipeline depth to suitable pipeline depth according to behavior of a running program. VSP can optimize energy at finer-grain than DVFS because pipeline scaling has a small overhead. In this paper, we fabricated a VSP processor chip using 180 nm technology and evaluated energy consumption of the chip. We present that the fabricated VSP chip dynamically varies the pipeline depth while a program is running and reduces the energy consumption at shorter interval than DVFS.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132741528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduction of Power Consumption in Key-specific AES Circuits","authors":"S. Matsuoka, S. Ichikawa","doi":"10.1109/ICNC.2012.61","DOIUrl":"https://doi.org/10.1109/ICNC.2012.61","url":null,"abstract":"If any inputs of the logic circuit are fixed to constants, the circuit can be optimized by reducing the logic gates (hardware specialization). This study reports the power consumption of AES cryptographic circuit, which was specialized for a fixed encryption key. We implemented this key-specific AES circuit with a Xilinx Virtex-5 FPGA, and measured the operational frequency, the logic scale, and the power consumption. The occupied slices were reduced to 64% of that of the original, while the reduction of power consumption was limited to 3.7%.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133250887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient Thread Recombining at Program Phase Changes","authors":"Kosuke Sobue, Tomoaki Tsumura, H. Matsuo","doi":"10.1109/ICNC.2012.59","DOIUrl":"https://doi.org/10.1109/ICNC.2012.59","url":null,"abstract":"Chip-multiprocessors now have become in wide use. For efficiently using the resources in chip-multiprocessors, programmers need to consider processor specifications and load balancing, but it is difficult for them. To address this problem, Thread Tailor has been proposed. Thread Tailor determines the number of threads based on processor specifications before execution, balances their loads based on the results of profiling and combines threads. However, Thread Tailor determines which threads should be combined based on only the number of executed cycles of each thread. Hence, the programs, whose threads change their computation loads according to program phases, may slow down with Thread Tailor. To solve this problem, we propose a method which dynamically recombines threads according to program phases for balancing the loads. The results of the experiment with SPLASH-2 benchmark suite and PARSEC benchmark suite show that the new method improves the execution time 6.0% in maximum.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Source Location Problems with Flow Requirements","authors":"K. Makino","doi":"10.1109/ICNC.2012.77","DOIUrl":"https://doi.org/10.1109/ICNC.2012.77","url":null,"abstract":"Location problems in networks are often formulated as optimization problems to determine the best location of facilities such as industrial plants or warehouses in given networks to satisfy a certain property. Source Location problems are the location problems based on flow (i.e., connectivity) requirements. In this paper, we briefly survey computational results for the problems.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123343944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
U. F. Siddiqi, Y. Shiraishi, Mona Abo El Dahb, S. M. Sait
{"title":"Finding Multi-Objective Shortest Paths Using Memory-Efficient Stochastic Evolution Based Algorithm","authors":"U. F. Siddiqi, Y. Shiraishi, Mona Abo El Dahb, S. M. Sait","doi":"10.1109/ICNC.2012.35","DOIUrl":"https://doi.org/10.1109/ICNC.2012.35","url":null,"abstract":"Multi-objective shortest path (MOSP) computation is a critical operation in many applications. MOSP problem aims to find optimal paths between source and destination nodes in a network. This paper presents a stochastic evolution (StocE) based algorithm for solving the MOSP problem. The proposed algorithm works on a single solution and is memory efficient than the evolutionary algorithms (EAs) that work on a population of solutions. In the proposed algorithm, different sub-paths in the solution are considered as its characteristics and bad sub paths are replaced by good sub-paths from generation to generation. The proposed algorithm is compared with non-dominated sorting genetic algorithm-II (NSGA-II), micro genetic algorithm (MicroGA), multi-objective simulated annealing (MOSA), and a straight-forward StocE. The comparison results show that the proposed algorithm generally performs better than the other algorithms that works on a single solution (i.e. MOSA and straight-forward StocE) and also infrequently performs better than the algorithms that work on a population of solutions (i.e. NSGA-II and MicroGA). Therefore, our proposed algorithm is suitable to solve MOSP in embedded systems that have a limited amount of memory.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mobile Agent Rendezvous on a Probabilistic Edge Evolving Ring","authors":"Yukiko Yamauchi, Tomoko Izumi, S. Kamei","doi":"10.1109/ICNC.2012.23","DOIUrl":"https://doi.org/10.1109/ICNC.2012.23","url":null,"abstract":"Rendezvous problem, which requires all mobile agents to gather on a single vertex, is one of the crucial methods for mobile agent systems. In previous studies on the rendezvous problem, mobile agents move on a static environment where the network topology does not change during the execution. However, in dynamic networks such as wireless mobile ad-hoc networks, the network continuously changes because of movements of vertices and interference of wireless signal. In this paper, we investigate the rendezvous problem in dynamic environment which is modeled by a probabilistic edge evolving graph. A probabilistic edge evolving graph is a sequence of sub graphs of an original graph G where each edge of G is contained in each sub graph probabilistically. We present a rendezvous algorithm for an evolving graph whose original graph is a ring, and its expected rendezvous time until two agents gather on a vertex. The analysis results show the impact of the initial directions to which agents start to move and the consistency of local port numbering during the execution on the expected rendezvous time.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117137577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recent Developments in Firing Squad Synchronization Algorithms: Smaller Solutions","authors":"H. Umeo","doi":"10.1109/ICNC.2012.72","DOIUrl":"https://doi.org/10.1109/ICNC.2012.72","url":null,"abstract":"Synchronizing large scale networks is an important and fundamental computing primitive in parallel and distributed systems. The synchronization in cellular automata has been known as the firing squad synchronization problem (FSSP). The FSSP has been studied extensively for more than forty years, and a rich variety of synchronization algorithms have been proposed so far. In the present paper, we construct a survey on recent developments in FSSP algorithms for not only one-dimensional but two-dimensional, even multi-dimensional cellular automata, focusing on smaller solutions to the FSSP.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123363299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fast Implementation of Matrix-matrix Product in Double-double Precision on NVIDIA C2050 and Application to Semidefinite Programming","authors":"Maho Nakata, Yasuyoshi Takao, S. Noda, R. Himeno","doi":"10.1109/ICNC.2012.19","DOIUrl":"https://doi.org/10.1109/ICNC.2012.19","url":null,"abstract":"We have implemented a fast double-double precision (has approx. 32 decimal significant digits) version of matrix-matrix multiplication routine called \"Rgemm\" of MPACK (http://mplapack.sourceforge.net/) on NVIDIA C2050 GPU. This routine is a higher precision version of gdgemmh in the BLAS (Basic Linear Algebra Subprograms) library. Our implementation is the fastest to date using NVIDIA C2050 and most efficient on NVIDIA GPUs, we achieved the peak performances of 16.4GFlops for the kernel performance (16.1GFlops with CPU-GPU transfer included), and 26.4GFlops (25.7GFlops with CPU-GPU transfer included) by employing lower accuracy arithmetic. These are 92.3% (90.7%) and 87.1% (84.8%) of the theoretical peak performance of NVIDIA C2050, which is about 150 times faster than the reference implementation on Intel Xeon X3470. Moreover, our implementations can handle arbitrary sizes of matrices by employing gPointer redirectingh technique by Nath et al. We integrated this GPU-accelerated version of Rgemm for double-double precision version of semi definite programming solver called SDPA-DD, and the performance improved at most 14.5 times. This version of Rgemm is available at http://mplapack.sourceforge.net/ since 2011/10/28.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Decidability Analysis of Some Classes of Extended Function Petri Net","authors":"A. Ohta, K. Tsuji","doi":"10.1109/ICNC.2012.79","DOIUrl":"https://doi.org/10.1109/ICNC.2012.79","url":null,"abstract":"In this report, we study liveness and reach ability problem of extended function Petri net with some structural restriction. Petri net is a mathematical model for concurrent systems such as parallel computers, manufacturing system, communication protocol and so on. Liveness and reach ability are important problems of Petri net. The former is to verify whether the system has no local deadlocks. The latter is to verify whether the system can reach the target status from the initial one. Extended function Petri net, where each arc weight is a function of the marking, has wide range of application including system biology, communication protocol and so on. However, it is hard to obtain theoretical results for general extended Petri net. First, we show liveness criterion of extended Petri net with asymmetric choice structure and extended free choice structure with some restricted arc functions. Then reach ability and liveness of extended Petri net with asymmetric choice structure is shown to be undecidable.","PeriodicalId":442973,"journal":{"name":"2012 Third International Conference on Networking and Computing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126886117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}