Reduction of Power Consumption in Key-specific AES Circuits

Abstract

If any inputs of the logic circuit are fixed to constants, the circuit can be optimized by reducing the logic gates (hardware specialization). This study reports the power consumption of AES cryptographic circuit, which was specialized for a fixed encryption key. We implemented this key-specific AES circuit with a Xilinx Virtex-5 FPGA, and measured the operational frequency, the logic scale, and the power consumption. The occupied slices were reduced to 64% of that of the original, while the reduction of power consumption was limited to 3.7%.