Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture

Abstract

Increase of energy consumption caused by processor enhancement has recently become a serious problem. Dynamic voltage and frequency scaling (DVFS) which dynamically lowers the supply voltage and clock frequency is widely used to reduce energy consumption. However, it is difficult to deliver fine-grain energy optimization by using DVFS because a voltage regulator takes a long time for scaling the voltage. To reduce energy consumption at fine-grain interval, we propose a variable stages pipeline (VSP) processor. VSP reduces energy consumption by dynamically varying the pipeline depth to suitable pipeline depth according to behavior of a running program. VSP can optimize energy at finer-grain than DVFS because pipeline scaling has a small overhead. In this paper, we fabricated a VSP processor chip using 180 nm technology and evaluated energy consumption of the chip. We present that the fabricated VSP chip dynamically varies the pipeline depth while a program is running and reduces the energy consumption at shorter interval than DVFS.