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[1990] Proceedings of the International Conference on Application Specific Array Processors最新文献

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Design of run-time fault-tolerant arrays of self-checking processing elements 自检处理元件运行时容错阵列的设计
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145453
J. Franzen
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引用次数: 2
Extensions to linear mapping for regular arrays with complex processing elements 对具有复杂处理元素的常规数组的线性映射的扩展
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145452
J. Rosseel, F. Catthoor, H. Man
{"title":"Extensions to linear mapping for regular arrays with complex processing elements","authors":"J. Rosseel, F. Catthoor, H. Man","doi":"10.1109/ASAP.1990.145452","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145452","url":null,"abstract":"The optimal architectural design of the processing elements (PEs) for an application specific regular array (RA) is nontrivial if the application has a complex operation set. The authors present an approach that extends the conventional, linear time-space transformation for such cases. In application-specific-integrated-circuit (ASIC) architectures, one has the freedom to fine-tune all aspects of the architecture to optimize the throughput. Therefore, the PEs can be designed to match the throughput and to optimize the area-cost of an RA architecture. The method presented allows a free design of the PEs with internal pipelining of the data paths, hardware sharing of operators among operations, multicycle operators, and interleaving of the execution of different index points. Compared to methods that allow only parts of these experiments, the local area-time tradeoffs are now explicitly incorporated in the global space-time assignment problem.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125594255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A feedback concentrator for the Image Understanding Architecture 一个用于图像理解架构的反馈集中器
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145494
D. Rana, C. Weems
{"title":"A feedback concentrator for the Image Understanding Architecture","authors":"D. Rana, C. Weems","doi":"10.1109/ASAP.1990.145494","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145494","url":null,"abstract":"The Image Understanding Architecture (IUA) is a massively parallel, multilevel system. The hardware implementation of two important summary feedback mechanisms-some/none response and count responders-for the lower two processing levels of the first generation IUA are described. Both mechanisms are implemented using multiple copies of a single custom VLSI chip. A brief overview of the custom chip is provided. The performance of the IUA's low-level processor with the feedback concentrator is compared to a similar mesh-connected parallel processor without the feedback concentrator mechanism and is shown to be significantly faster. An overview of the plants for the feedback concentrator for the second generation IUA is provided.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Channel complexity analysis for reconfigurable VLSI/WSI processor arrays 可重构VLSI/WSI处理器阵列的信道复杂度分析
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145470
P. Rhee, J. H. Kim
{"title":"Channel complexity analysis for reconfigurable VLSI/WSI processor arrays","authors":"P. Rhee, J. H. Kim","doi":"10.1109/ASAP.1990.145470","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145470","url":null,"abstract":"The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned logical cells are determined. A domain may be decided considering predetermined maximum distance between two logically adjacent cells. Interconnection redundancy, is represented by channel complexity, where channel complexity is measured by the number of tracks and associated switches. The array is partitioned into as small units, called subranges, as possible while preserving the characteristics of array reconfigurability. Channel complexity is analyzed based on subranges.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115310460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The bit-serial systolic back-projection engine (BSSBPE) 位串行收缩反投影引擎(BSSBPE)
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145442
R. Bayford
{"title":"The bit-serial systolic back-projection engine (BSSBPE)","authors":"R. Bayford","doi":"10.1109/ASAP.1990.145442","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145442","url":null,"abstract":"The author presents a machine designed with a two-phase approach. First, the selection of an efficient algorithm, based on the quality of the final image and on the computational efficiency, is undertaken. Second, the algorithm is realized in hardware which incorporates efficient array processing structures, with the aim of creating regular repeated structures. The design is based on the S.Y. Kung and C.E. Leiserson (1978) approach, although certain elements of the architecture deviate from a true systolic architecture. These include bidirectional communication, which allows other image processing operations to be performed. The bit-serial machine is designed to perform the image reconstruction operation known as back-projection. The machine offers significant speed improvement over the general-purpose pipeline architectures used at present.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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