Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

Abstract

The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned logical cells are determined. A domain may be decided considering predetermined maximum distance between two logically adjacent cells. Interconnection redundancy, is represented by channel complexity, where channel complexity is measured by the number of tracks and associated switches. The array is partitioned into as small units, called subranges, as possible while preserving the characteristics of array reconfigurability. Channel complexity is analyzed based on subranges.<>