The bit-serial systolic back-projection engine (BSSBPE)

The author presents a machine designed with a two-phase approach. First, the selection of an efficient algorithm, based on the quality of the final image and on the computational efficiency, is undertaken. Second, the algorithm is realized in hardware which incorporates efficient array processing structures, with the aim of creating regular repeated structures. The design is based on the S.Y. Kung and C.E. Leiserson (1978) approach, although certain elements of the architecture deviate from a true systolic architecture. These include bidirectional communication, which allows other image processing operations to be performed. The bit-serial machine is designed to perform the image reconstruction operation known as back-projection. The machine offers significant speed improvement over the general-purpose pipeline architectures used at present.<>